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teacher_uart

  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-09-26
  • Size : 1.84mb
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  • Author :abc****
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Introduction - If you have any usage issues, please Google them yourself
The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3
Packet file list
(Preview for download)
FilenameSizeUpdate
teacher_uart\teacher_uart\project3.cache\wt\gui_handlers.wdf 3884 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\java_command_handlers.wdf 1610 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\project.wpc 122 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\synthesis.wdf 5390 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\synthesis_details.wdf 100 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\webtalk_pa.xml 4565 2018-06-01
teacher_uart\teacher_uart\project3.cache\wt\xsim.wdf 256 2018-06-01
teacher_uart\teacher_uart\project3.hw\hw_1\hw.xml 835 2018-06-01
teacher_uart\teacher_uart\project3.hw\project3.lpr 343 2018-06-01
teacher_uart\teacher_uart\project3.hw\webtalk\.xsim_webtallk.info 59 2018-06-20
teacher_uart\teacher_uart\project3.ip_user_files\README.txt 130 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_1.xml 212 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_10.xml 228 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_2.xml 226 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_3.xml 233 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_4.xml 411 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_5.xml 233 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_6.xml 233 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_7.xml 235 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_8.xml 214 2018-06-01
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_9.xml 214 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.init_design.begin.rst 182 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.init_design.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.opt_design.begin.rst 182 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.opt_design.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.place_design.begin.rst 182 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.place_design.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.route_design.begin.rst 182 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.route_design.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.vivado.begin.rst 182 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.vivado.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\.Vivado_Implementation.queue.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\gen_run.xml 5186 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\htr.txt 401 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\init_design.pb 3730 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\ISEWrap.js 7308 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\ISEWrap.sh 1623 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\opt_design.pb 7442 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\place_design.pb 11723 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\project.wdf 3634 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\route_design.pb 11216 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\rundef.js 1394 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\runme.bat 229 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\runme.log 21246 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\runme.sh 1254 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top.tcl 5167 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top.vdi 21169 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_clock_utilization_routed.rpt 15396 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_control_sets_placed.rpt 4276 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_opted.pb 37 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_opted.rpt 4540 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_opted.rpx 5865 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_routed.pb 37 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_routed.rpt 4544 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_drc_routed.rpx 5866 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_io_placed.rpt 73831 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_methodology_drc_routed.pb 52 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_methodology_drc_routed.rpt 9379 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_methodology_drc_routed.rpx 12796 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_opt.dcp 135495 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_placed.dcp 153181 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_power_routed.rpt 7785 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_power_routed.rpx 41521 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_power_summary_routed.pb 722 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_routed.dcp 165631 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_route_status.pb 43 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_route_status.rpt 588 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_timing_summary_routed.rpt 7444 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_timing_summary_routed.rpx 8676 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_utilization_placed.pb 276 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\uart_top_utilization_placed.rpt 8922 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\vivado.jou 704 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\vivado.pb 149 2018-06-01
teacher_uart\teacher_uart\project3.runs\impl_1\write_bitstream.pb 7086 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\.vivado.begin.rst 181 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\.vivado.end.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\.Vivado_Synthesis.queue.rst 0 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\.Xil\uart_top_propImpl.xdc 1052 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\gen_run.xml 2295 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\htr.txt 393 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\ISEWrap.js 7308 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\ISEWrap.sh 1623 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\project.wdf 3634 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\rundef.js 1323 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\runme.bat 229 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\runme.log 50640 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\runme.sh 1191 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\uart_top.dcp 27159 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\uart_top.tcl 2411 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\uart_top.vds 25273 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\uart_top_utilization_synth.pb 276 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\uart_top_utilization_synth.rpt 7260 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\vivado.jou 699 2018-06-01
teacher_uart\teacher_uart\project3.runs\synth_1\vivado.pb 41107 2018-06-01
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\compile.bat 832 2018-06-01
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\compile.log 0 2018-06-01
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\elaborate.bat 909 2018-06-01
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\elaborate.log 1050 2018-06-01
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\glbl.v 1474 2017-12-14
teacher_uart\teacher_uart\project3.sim\sim_1\behav\xsim\simulate.bat 795 2018-06-01
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