SD card controller can just read data using 1 bit SD mode. I have written this core for nios 2 CPU, Cyclone, but I think it can works With other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and The CPU clock is 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck - SD card controller can just read the data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. The Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the thewire 1:5). If you have a wish you can on your this core. Good luck

Packet : 57578844sd_ip.rar filelist
sd卡读写IP\sd\class.ptf
sd卡读写IP\sd\crc_unit_16.v
sd卡读写IP\sd\crc_unit_7.v
sd卡读写IP\sd\inc\altera_avalon_camelot_sd_controller_regs.h
sd卡读写IP\sd\inc
sd卡读写IP\sd\mk_user_logic_Camelot_SD_Controller.pl
sd卡读写IP\sd\readme.txt
sd卡读写IP\sd\sd.v
sd卡读写IP\sd\sd_controller.v
sd卡读写IP\sd\sd_host.v
sd卡读写IP\sd\soft example for nios2\main.cpp
sd卡读写IP\sd\soft example for nios2
sd卡读写IP\sd
sd卡读写IP

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