With asynchronous and synchronous clock clearance 0 enabled four adder counter with count enable, asynchronous reset and preset functions of numerical parallel adder four counters, by the experiment shown in Figure 1, Figure 4 middle latch rst is asynchronous clearance signal, high effective signal clk is Latched D [3 .. 0] is 4-bit data input. When ENA for 1:00, MUX will increase the output value of 1 load in latch data terminal when the ENA for the 0:00 to 0000 add-in latch.

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