Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered

Packet : 95302942clock.rar filelist
多功能时钟\clk.v
多功能时钟\clock.v
多功能时钟\delay.v
多功能时钟\display.v
多功能时钟\fdiv.v
多功能时钟\fdiv_ms.v
多功能时钟\key_press.v
多功能时钟\时钟文档.doc
多功能时钟

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