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Verilog数字VLSI设计教程（源码）

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  • Update : 2019-04-22
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Verilog Digital VLSI Design Course Official Lab
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Verilog数字VLSI设计教程 0 2016-04-22
Verilog数字VLSI设计教程\Lab01 0 2013-09-10
Verilog数字VLSI设计教程\Lab01\AndOr.v 500 2005-01-28
Verilog数字VLSI设计教程\Lab01\Intro_Top.sct 1988 2008-01-18
Verilog数字VLSI设计教程\Lab01\Intro_Top.spj 1147 2005-02-15
Verilog数字VLSI设计教程\Lab01\Intro_Top.v 1288 2005-09-21
Verilog数字VLSI设计教程\Lab01\Intro_Top.vcs 56 2005-01-28
Verilog数字VLSI设计教程\Lab01\Lab01_Ans 0 2013-09-10
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\AndOr.v 500 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\default.cfg 1382 2007-01-31
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Netlist.v 1028 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Top.sct 1990 2008-01-18
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Top.SDF 2980 2007-11-20
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Top.spj 1147 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Top.v 1288 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_Top.vcs 56 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_TopFlat.sdf 3795 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\Intro_TopFlat.v 609 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\SR.v 741 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\TestBench.v 1633 2007-09-19
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\VCS_SimRun.VCD 1598 2007-11-20
Verilog数字VLSI设计教程\Lab01\Lab01_Ans\XorNor.v 665 2007-09-19
Verilog数字VLSI设计教程\Lab01\SR.v 741 2005-04-10
Verilog数字VLSI设计教程\Lab01\TestBench.v 1633 2005-08-23
Verilog数字VLSI设计教程\Lab01\XorNor.v 665 2007-09-19
Verilog数字VLSI设计教程\Lab02 0 2013-09-10
Verilog数字VLSI设计教程\Lab02\Lab02_Ans 0 2013-09-10
Verilog数字VLSI设计教程\Lab02\Lab02_Ans\default.cfg 1204 2007-09-19
Verilog数字VLSI设计教程\Lab02\Lab02_Ans\Extend.spj 559 2005-02-15
Verilog数字VLSI设计教程\Lab02\Lab02_Ans\Extend.v 1224 2005-11-03
Verilog数字VLSI设计教程\Lab02\Lab02_Ans\Vector.spj 869 2005-02-15
Verilog数字VLSI设计教程\Lab02\Lab02_Ans\Vector.v 1288 2007-09-19
Verilog数字VLSI设计教程\Lab03 0 2013-09-10
Verilog数字VLSI设计教程\Lab03\Converter.v 1217 2005-02-01
Verilog数字VLSI设计教程\Lab03\Counter.spj 1105 2005-02-15
Verilog数字VLSI设计教程\Lab03\Counter.v 1510 2005-08-24
Verilog数字VLSI设计教程\Lab03\Lab03_Ans 0 2013-09-10
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Integers.spj 795 2005-02-15
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Integers.v 1636 2005-01-28
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01 0 2013-09-10
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\Converter.v 1217 2005-02-01
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\Counter.v 1510 2005-08-24
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTop.v 3628 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_Area.sdf 21367 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_Area.v 3406 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_pPad12_Area.sdf 24032 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_pPad12_Area.v 3941 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_Speed.sdf 22206 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTopNetlist_Speed.v 3456 2007-09-19
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTop_Area.sct 1851 2008-01-11
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTop_Speed.sct 1850 2008-01-11
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Step01\ParamCounterTop_Step1_pPad12_Area.sct 1743 2008-01-11
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Truncate.spj 716 2005-02-15
Verilog数字VLSI设计教程\Lab03\Lab03_Ans\Truncate.v 1722 2005-12-17
Verilog数字VLSI设计教程\Lab03\ParamCounterFiles.vcs 46 2005-02-01
Verilog数字VLSI设计教程\Lab03\ParamCounterTop.spj 1105 2005-02-15
Verilog数字VLSI设计教程\Lab03\ParamCounterTop.v 3628 2007-09-19
Verilog数字VLSI设计教程\Lab03\ParamCounterTop_Step1.sct 1710 2008-01-11
Verilog数字VLSI设计教程\Lab04 0 2013-09-10
Verilog数字VLSI设计教程\Lab04\Lab04_Ans 0 2013-09-10
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03 0 2013-09-10
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\FlipFlops.sct 2144 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\FlipFlops.spj 881 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\FlipFlops.v 3388 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\FlipFlopsNetlist_AreaHigh.v 817 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\Latches.sct 1296 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\Latches.spj 788 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\Latches.v 3787 2007-09-25
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\LatchesNetlist_AreaHigh.v 917 2007-09-26
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\SyncClearFlipFlop.sct 1480 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\SyncClearFlipFlop.spj 671 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\SyncClearFlipFlop.v 1517 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step01_03\SyncClearFlipFlopNetlist_AreaHigh.v 269 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04 0 2013-09-10
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\default.cfg 1290 2007-01-30
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\Mux2.v 545 2007-01-30
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftReg.spj 762 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegister.v 2939 2007-01-30
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegister.vcs 38 2007-01-30
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterArea.sct 1548 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterNetlistArea.sdf 11399 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterNetlistArea.v 3100 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterNetlistSpeed.sdf 11614 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterNetlistSpeed.v 3123 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\SerShiftRegisterSpeed.sct 1661 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step04\ShiftFlop.v 717 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05 0 2013-09-10
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\default.cfg 1433 2007-01-31
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\Mux3.v 614 2007-01-31
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftReg.spj 1033 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegister.v 3615 2007-01-31
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegister.vcs 38 2007-01-31
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterArea.sct 1519 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterNetlistArea.sdf 14382 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterNetlistArea.v 3890 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterNetlistSpeed.sdf 14362 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterNetlistSpeed.v 3890 2007-09-19
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ParShiftRegisterSpeed.sct 1661 2008-01-18
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step05\ShiftFlop.v 717 2005-02-15
Verilog数字VLSI设计教程\Lab04\Lab04_Ans\Step06 0 2013-09-10
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