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实验一多路选择器与CPU辅助模块设计

  • Category : VHDL-FPGA-Verilog
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  • Update : 2019-05-04
  • Size : 33.2mb
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  • Author :陈***
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Solutions for computer experiment.
Packet file list
(Preview for download)
FilenameSizeUpdate
org01_20190226 0 2019-02-26
org01_20190226\Arduino-Sword-002NEW.pptx 1475381 2018-03-06
org01_20190226\Element 0 2019-02-26
org01_20190226\Element.pdf 69645 2016-02-25
org01_20190226\Element\add_32.v 628 2016-02-25
org01_20190226\Element\addc_32.v 811 2016-02-25
org01_20190226\Element\and32.v 629 2016-02-25
org01_20190226\Element\Ext_imm16.v 629 2016-02-25
org01_20190226\Element\MUX2T1_32.v 686 2016-02-25
org01_20190226\Element\MUX2T1_5.v 683 2016-02-25
org01_20190226\Element\MUX2T1_64.v 691 2016-02-25
org01_20190226\Element\MUX2T1_8.v 681 2016-02-25
org01_20190226\Element\MUX4T1_32.v 815 2016-02-25
org01_20190226\Element\MUX4T1_5.v 803 2016-02-25
org01_20190226\Element\MUX8T1_32.v 948 2016-02-25
org01_20190226\Element\MUX8T1_8.v 939 2016-02-25
org01_20190226\Element\nor32.v 625 2016-02-25
org01_20190226\Element\or_bit_32 .v 637 2016-02-25
org01_20190226\Element\or32.v 622 2016-02-25
org01_20190226\Element\SignalExt_32.v 632 2016-02-25
org01_20190226\Element\srl32.v 709 2016-02-25
org01_20190226\Element\xor32.v 624 2016-02-25
org01_20190226\Exp01.ucf 4958 2016-02-26
org01_20190226\ngc 0 2019-02-26
org01_20190226\ngc\clk_div.v 828 2015-06-27
org01_20190226\ngc\Multi_8CH32.ngc 61386 2015-12-29
org01_20190226\ngc\Multi_8CH32_IO.v 1120 2015-12-29
org01_20190226\ngc\ok.ucf 5159 2016-03-03
org01_20190226\ngc\PIO.ngc 8178 2015-12-29
org01_20190226\ngc\PIO_IO.v 733 2015-12-29
org01_20190226\ngc\RAM.coe 83 2016-02-25
org01_20190226\ngc\ROM.coe 416 2016-02-25
org01_20190226\ngc\SAnti_jitter.ngc 91851 2015-12-28
org01_20190226\ngc\SAnti_jitter_IO.v 941 2015-12-28
org01_20190226\ngc\Seg7_Dev.ngc 16843 2016-01-02
org01_20190226\ngc\Seg7_Dev_IO.v 713 2016-01-02
org01_20190226\ngc\SEnter_2_32.ngc 38450 2015-12-28
org01_20190226\ngc\SEnter_2_32_IO.v 966 2015-12-30
org01_20190226\ngc\SPIO.ngc 19020 2015-12-28
org01_20190226\ngc\SPIO_IO.v 1163 2016-01-01
org01_20190226\ngc\SSeg7_Dev.ngc 99256 2015-12-28
org01_20190226\ngc\SSeg7_Dev_IO.v 1020 2016-01-01
org01_20190226\OExp01.pdf 169025 2016-02-25
org01_20190226\ok.ucf 5159 2016-03-03
org01_20190226\sym 0 2019-02-26
org01_20190226\sym\clk_div.sym 1701 2015-12-27
org01_20190226\sym\HexTo8SEG.sym 1695 2015-12-28
org01_20190226\sym\MC14495_ZJU.sym 3563 2015-10-25
org01_20190226\sym\Multi_8CH32.sym 4756 2015-11-08
org01_20190226\sym\MUX2T1_64.sym 1393 2015-07-02
org01_20190226\sym\MUX2T1_8.sym 1372 2015-12-28
org01_20190226\sym\MUX8T1_8.sym 2896 2015-12-29
org01_20190226\sym\P2S.sym 2318 2016-01-02
org01_20190226\sym\parallel2serial.sym 2231 2015-12-28
org01_20190226\sym\PIO.sym 2237 2015-12-27
org01_20190226\sym\RAM_B.sym 1619 2016-01-01
org01_20190226\sym\ROM_D.sym 900 2016-01-01
org01_20190226\sym\SAnti_jitter.sym 3750 2015-12-27
org01_20190226\sym\ScanSync.sym 2443 2015-11-06
org01_20190226\sym\Seg_map.sym 1186 2015-12-28
org01_20190226\sym\Seg7_Dev.sym 2450 2016-01-02
org01_20190226\sym\SEnter_2_32.sym 2774 2015-12-27
org01_20190226\sym\SPIO.sym 3415 2015-12-28
org01_20190226\sym\SSeg_map.sym 989 2015-12-28
org01_20190226\sym\SSeg7_Dev.sym 3345 2015-12-28
org01_20190226\实验一-多路选择器与CPU辅助模块设计2019.pptx 33272182 2019-02-26
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