VHDL implementation of spi interface, and the device and IP for xilinx -spi interface VHDL realize, by IP for xilinx devices and the

Packet : 39709601spi.rar filelist
spi\spi_controller\spi_controller.ise
spi\spi_controller\templates\coregen.xml
spi\spi_controller\spi_controller.restore
spi\spi_controller\xst\work\sub00\vhpl00.vho
spi\spi_controller\xst\work\sub00\vhpl01.vho
spi\spi_controller\xst\work\sub00\vhpl02.vho
spi\spi_controller\xst\work\sub00\vhpl03.vho
spi\spi_controller\xst\work\sub00\vhpl04.vho
spi\spi_controller\xst\work\sub00\vhpl05.vho
spi\spi_controller\xst\work\sub00\vhpl06.vho
spi\spi_controller\xst\work\sub00\vhpl07.vho
spi\spi_controller\xst\work\hdllib.ref
spi\spi_controller\xst\work\hdpdeps.ref
spi\spi_controller\xst\dump.xst\spi_controller.prj\ntrc.scr
spi\spi_controller\xst\dump.xst\spi_interface.prj\ntrc.scr
spi\spi_controller\uart232\doc\spi4_2_lite_ds502.pdf
spi\spi_controller\uart232\doc\spi4_2_lite_gsg182.pdf
spi\spi_controller\uart232\doc\spi4_2_lite_ug181.pdf
spi\spi_controller\uart232\spi4_2_lite_release_notes.txt
spi\spi_controller\shift_1.vhd
spi\spi_controller\shift_1.vho
spi\spi_controller\shift_1.v
spi\spi_controller\shift_1.veo
spi\spi_controller\shift_1.asy
spi\spi_controller\shift_1.sym
spi\spi_controller\shift_1.ngc
spi\spi_controller\shift_1.xco
spi\spi_controller\shift_1_xmdf.tcl
spi\spi_controller\shift_1_flist.txt
spi\spi_controller\shift_1_readme.txt
spi\spi_controller\shift_2.vhd
spi\spi_controller\_xmsgs\xst.xmsgs
spi\spi_controller\spi_controller.ise_ISE_Backup
spi\spi_controller\spi_interface.sch
spi\spi_controller\spi_interface.jhd
spi\spi_controller\spi_interface.schcmd
spi\spi_controller\shift_2.vho
spi\spi_controller\shift_2.v
spi\spi_controller\shift_2.veo
spi\spi_controller\shift_2.asy
spi\spi_controller\shift_2.sym
spi\spi_controller\shift_2.ngc
spi\spi_controller\shift_2.xco
spi\spi_controller\shift_2_xmdf.tcl
spi\spi_controller\shift_2_flist.txt
spi\spi_controller\shift_2_readme.txt
spi\spi_controller\spi_interface_summary.html
spi\spi_controller\spi_interface.vhf
spi\spi_controller\spi_interface.syr
spi\spi_controller\spi_interface.lso
spi\spi_controller\spi_interface_vhdl.prj
spi\spi_controller\spi_interface.stx
spi\spi_controller\spi_controller.ntrc_log
spi\spi_controller\spi_interface.ngc
spi\spi_controller\coregen_lock
spi\spi_controller\spi_interface.ngr
spi\spi_controller\spi_controller.spl
spi\spi_controller\pepExtractor.prj
spi\spi_controller\spi_controller.sym
spi\spi_controller\spi_interface.cmd_log
spi\spi_controller\spi_interface.schbak
spi\spi_controller\spi_interface.prj
spi\spi_controller\spi_interface.xst
spi\spi_controller\spi_controller.vhd
spi\spi_controller\spi_controller_summary.html
spi\spi_controller\tmp\_cg\xil_3624_48.in
spi\spi_controller\tmp\_cg\uart232_pl4_lite_src_top.ngc
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top.veo
spi\spi_controller\tmp\_cg\uart232_pl4_lite_src_top.veo
spi\spi_controller\tmp\_cg\uart232\example_design\pl4_lite_fifo_loopback_read.v
spi\spi_controller\tmp\_cg\uart232\example_design\pl4_lite_fifo_loopback.v
spi\spi_controller\tmp\_cg\uart232\example_design\pl4_lite_fifo_loopback_write.v
spi\spi_controller\tmp\_cg\uart232\example_design\pl4_lite_src_clk.v
spi\spi_controller\tmp\_cg\uart232\example_design\pl4_lite_snk_clk.v
spi\spi_controller\tmp\_cg\uart232\example_design\uart232_pl4_lite_snk_top.v
spi\spi_controller\tmp\_cg\uart232\example_design\uart232_pl4_lite_src_top.v
spi\spi_controller\tmp\_cg\uart232\example_design\virtex4.v
spi\spi_controller\tmp\_cg\uart232\example_design\uart232_top.v
spi\spi_controller\tmp\_cg\uart232\example_design\uart232_top.ucf
spi\spi_controller\tmp\_cg\uart232\simulation\data_file.dat
spi\spi_controller\tmp\_cg\uart232\simulation\glbl.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_clk_gen.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_data_monitor.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_demo_testbench.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_procedures.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_startup.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_status_monitor.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_stimulus.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_testcase_pkg.v
spi\spi_controller\tmp\_cg\uart232\simulation\pl4_lite_testcase.v
spi\spi_controller\tmp\_cg\uart232\simulation\functional\simulate_mti.do
spi\spi_controller\tmp\_cg\uart232\simulation\functional\wave_mti.do
spi\spi_controller\tmp\_cg\uart232\simulation\snk_calendar.dat
spi\spi_controller\tmp\_cg\uart232\simulation\src_calendar.dat
spi\spi_controller\tmp\_cg\_bbx\uart232_pl4_lite_snk_top.prj
spi\spi_controller\tmp\_cg\_bbx\uart232_pl4_lite_snk_top.scr
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_pkg.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\srl_pipe.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\generic_fifo_pkg.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\rloc_package.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\dip4_calc.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_1shot_rising.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_fifo_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_it.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\running_crc.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\crc.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_reg_gray.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_ram.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_ram_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_rd.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_sync.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_synchronizer.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr_par.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr64.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_afifo.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_core.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr0.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr1.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_buffer.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_top.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_top_user_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_synchronizer.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_reg_gray.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_rd.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_fifo_64.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_dip2.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo_trns.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_proc.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_trns.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_write.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_write_64.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_payload.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_barrel.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_dip4.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_train_create.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_core.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_core_64.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ce.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ddr0.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ddr1.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_master_addr.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_master_trans.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_slave_addr.vhd
spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_slave_trans.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_pkg.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\srl_pipe.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\generic_fifo_pkg.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\rloc_package.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\dip4_calc.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_sync_1shot_rising.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_sync_fifo_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_sync_it.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\pl4_lite_sync_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\running_crc.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\common\crc.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo_reg_gray.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo_ram.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo_ram_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo_rd.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_generic_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_sync.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_synchronizer.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_wr_par.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_wr64.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_afifo.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_core.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr0.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr1.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_io_buffer.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_io.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_top.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\snk\pl4_lite_snk_top_user_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_reset.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_synchronizer.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo_reg_gray.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram_v5.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo_rd.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo_wr.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_async_burst_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_fifo_64.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal_dip2.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo_trns.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal_proc.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal_trns.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_cal.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_write.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_write_64.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_data_payload.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_data_barrel.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_data_dip4.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_data.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_train_create.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_core.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_core_64.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_io_ce.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_io_ddr0.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_io_ddr1.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_io.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_clk.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_top_master_addr.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_top_master_trans.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_top_slave_addr.vhd
spi\spi_controller\tmp\_cg\_bbx\_xlp\pl4_lite_v4_2\src\pl4_lite_src_top_slave_trans.vhd
spi\spi_controller\tmp\_cg\_bbx\uart232_pl4_lite_snk_top.vhd
spi\spi_controller\tmp\_cg\_bbx\uart232_pl4_lite_snk_top_xst.log
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl00.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl01.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl02.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl03.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl04.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl05.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl06.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl07.vho
spi\spi_controller\tmp\_cg\uart232_pl4_lite_snk_top_xsd\pl4_lite_v4_2\sub00\vhpl08.vho
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