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test_ADC

  • Category : VHDL-FPGA-Verilog
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  • Update : 2019-11-20
  • Size : 12.05mb
  • Downloaded :0次
  • Author :白***
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transition of A/D signal
Packet file list
(Preview for download)
FilenameSizeUpdate
test_ADC 0 2019-11-10
test_ADC\test_ADC.cache 0 2019-11-09
test_ADC\test_ADC.cache\compile_simlib 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\activehdl 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\ies 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\modelsim 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\questa 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\riviera 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\vcs 0 2019-11-07
test_ADC\test_ADC.cache\compile_simlib\xcelium 0 2019-11-07
test_ADC\test_ADC.cache\ip 0 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2 0 2019-11-10
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e.logs 0 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e.logs\runme.log 31126 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e 0 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\8162bc2d1b3f291e.xci 12784 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\blk_mem_gen_0.dcp 26494 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\blk_mem_gen_0_sim_netlist.v 28882 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\blk_mem_gen_0_sim_netlist.vhdl 44527 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\blk_mem_gen_0_stub.v 1337 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\blk_mem_gen_0_stub.vhdl 1472 2019-11-08
test_ADC\test_ADC.cache\ip\2018.2\8162bc2d1b3f291e\stats.txt 111 2019-11-08
test_ADC\test_ADC.cache\wt 0 2019-11-07
test_ADC\test_ADC.cache\wt\gui_handlers.wdf 12261 2019-11-10
test_ADC\test_ADC.cache\wt\java_command_handlers.wdf 3246 2019-11-10
test_ADC\test_ADC.cache\wt\project.wpc 122 2019-11-10
test_ADC\test_ADC.cache\wt\synthesis.wdf 5382 2019-11-10
test_ADC\test_ADC.cache\wt\synthesis_details.wdf 100 2019-11-10
test_ADC\test_ADC.cache\wt\webtalk_pa.xml 10459 2019-11-10
test_ADC\test_ADC.cache\wt\xsim.wdf 239 2019-11-10
test_ADC\test_ADC.hw 0 2019-11-10
test_ADC\test_ADC.hw\hw_1 0 2019-11-07
test_ADC\test_ADC.hw\hw_1\hw.xml 782 2019-11-10
test_ADC\test_ADC.hw\hw_1\wave 0 2019-11-07
test_ADC\test_ADC.hw\test_ADC.lpr 343 2019-11-07
test_ADC\test_ADC.ip_user_files 0 2019-11-09
test_ADC\test_ADC.ip_user_files\ip 0 2019-11-08
test_ADC\test_ADC.ip_user_files\ip\blk_mem_gen_0 0 2019-11-10
test_ADC\test_ADC.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.veo 2983 2019-11-10
test_ADC\test_ADC.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.vho 3226 2019-11-10
test_ADC\test_ADC.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.v 1276 2019-11-08
test_ADC\test_ADC.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.vhdl 1355 2019-11-08
test_ADC\test_ADC.ip_user_files\ipstatic 0 2019-11-08
test_ADC\test_ADC.ip_user_files\ipstatic\simulation 0 2019-11-08
test_ADC\test_ADC.ip_user_files\ipstatic\simulation\blk_mem_gen_v8_4.v 171256 2019-11-08
test_ADC\test_ADC.ip_user_files\mem_init_files 0 2019-11-10
test_ADC\test_ADC.ip_user_files\mem_init_files\blk_mem_gen_0.mif 2304 2019-11-10
test_ADC\test_ADC.ip_user_files\mem_init_files\sine.coe 792 2019-11-10
test_ADC\test_ADC.ip_user_files\mem_init_files\summary.log 899 2019-11-08
test_ADC\test_ADC.ip_user_files\README.txt 130 2019-11-07
test_ADC\test_ADC.ip_user_files\sim_scripts 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.mif 2304 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.sh 4959 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.udo 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\compile.do 694 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\file_info.txt 441 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\glbl.v 1474 2018-06-15
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\README.txt 2201 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\simulate.do 340 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\sine.coe 792 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\summary.log 899 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\wave.do 32 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.mif 2304 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.sh 5713 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\file_info.txt 441 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\glbl.v 1474 2018-06-15
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\README.txt 2142 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\run.f 501 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\sine.coe 792 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\ies\summary.log 899 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.mif 2304 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.sh 5119 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\blk_mem_gen_0.udo 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\compile.do 778 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\file_info.txt 441 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\glbl.v 1474 2018-06-15
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\README.txt 2201 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\simulate.do 341 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\sine.coe 792 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\summary.log 899 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\modelsim\wave.do 32 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.mif 2304 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.sh 5230 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\blk_mem_gen_0.udo 0 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\compile.do 744 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\elaborate.do 213 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\file_info.txt 441 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\glbl.v 1474 2018-06-15
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\README.txt 2201 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\simulate.do 203 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\sine.coe 792 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\summary.log 899 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\questa\wave.do 32 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\README.txt 3236 2019-11-08
test_ADC\test_ADC.ip_user_files\sim_scripts\blk_mem_gen_0\riviera 0 2019-11-08
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