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通信协议FPGA

  • Category : VHDL-FPGA-Verilog
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  • Update : 2020-02-25
  • Size : 18.7mb
  • Downloaded :0次
  • Author :蔺****
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Introduction - If you have any usage issues, please Google them yourself
This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.
Packet file list
(Preview for download)
FilenameSizeUpdate
class_homework 0 2019-12-20
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class_homework\EasyChipBase_20190516\_ngo 0 2019-12-26
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class_homework\EasyChipBase_20190516\_ngo\cs_ila_pro_0\ila_pro_0.vho 1475 2019-12-24
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class_homework\EasyChipBase_20190516\_ngo\cs_ila_pro_0\ila_pro_0_flist.txt 225 2019-12-24
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class_homework\EasyChipBase_20190516\_ngo\cs_ila_pro_0\ila_pro_0.xise 41266 2019-12-24
class_homework\EasyChipBase_20190516\_ngo\cs_ila_pro_0\coregen.log 2454 2019-12-24
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class_homework\EasyChipBase_20190516\isim\tb_data_send_isim_beh.exe.sim\libPortability.dll 901632 2013-10-13
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