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课程设计-数字钟

  • Category : VHDL-FPGA-Verilog
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  • Update : 2020-05-18
  • Size : 13.13mb
  • Downloaded :0次
  • Author :peen*****
  • About : Nobody
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Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch
Packet file list
(Preview for download)
FilenameSizeUpdate
课程设计-陶进凡_潘杰辉_谢育锋 0 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\bell.vhd 1222 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\jishi.vhd 4904 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\juzhen.vhd 4588 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\miaobiao.vhd 2907 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\naozhong.vhd 3127 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\shuzizhong320.dpf 239 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\shuzizhong320.pin 33300 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\xianshi.vhd 5301 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\xiaodou.vhd 1558 2020-03-21
课程设计-陶进凡_潘杰辉_谢育锋\数字钟演示视频.mp4 13360686 2020-03-23
课程设计-陶进凡_潘杰辉_谢育锋\课程设计-数字钟.docx 574571 2020-05-18
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