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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2020-06-17
  • Size : 1.72mb
  • Downloaded :1次
  • Author :goth****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed
Packet file list
(Preview for download)
FilenameSizeUpdate
CNN 0 2019-12-17
CNN\Addr_cal.v 847 2019-11-29
CNN\cnn_post.v 43957 2019-12-03
CNN\cnn设计报告.docx 1983259 2019-12-11
CNN\convolution.v 321 2019-12-11
CNN\ctrl.v 1466 2019-11-29
CNN\Data_reg.v 151 2019-11-29
CNN\image.txt 638 2019-11-29
CNN\mem.v 394 2019-11-29
CNN\mux1.v 306 2019-11-29
CNN\pixel_cnt.v 1283 2019-11-28
CNN\pool.v 409 2019-11-29
CNN\simple_conv_pool.v 1180 2019-11-29
CNN\simple_conv_pool_P.v 47297 2019-12-03
CNN\tb.v 462 2019-12-11
CNN\tb_p.v 521 2019-12-03
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