As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.

Packet : 107215809show_your_student_id_number_co-design_of_c_and_verilog.rar filelist
show your student ID number\CCode\col.dat
show your student ID number\CCode\col.dat.bak
show your student ID number\CCode\Debug
show your student ID number\CCode\scan.dat
show your student ID number\CCode\show.cpp
show your student ID number\CCode\show.dsp
show your student ID number\CCode\show.dsw
show your student ID number\CCode\show.ncb
show your student ID number\CCode\show.opt
show your student ID number\CCode\show.plg
show your student ID number\CCode
show your student ID number\hw4.doc
show your student ID number\verilog\col.dat
show your student ID number\verilog\readme.doc
show your student ID number\verilog\scan.dat
show your student ID number\verilog\showFpga_tb.v
show your student ID number\verilog\showid.v
show your student ID number\verilog
show your student ID number

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