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  • Category : VHDL-FPGA-Verilog
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  • Update : 2020-11-10
  • Size : 3.75mb
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  • Author :li~***
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Introduction - If you have any usage issues, please Google them yourself
SPI serial port simple data communication experiment, to achieve data transmission
Packet file list
(Preview for download)
FilenameSizeUpdate
7\design\spi_ctrl.v 3708 2015-05-16
7\documents\dac3283.pdf 1783377 2012-07-19
7\documents\ex_spi状态迁移图.pdf 25392 2015-05-12
7\documents\ex_spi状态迁移图.vsdx 20573 2015-05-12
7\documents\SPI接口时序仿真.pptx 665753 2014-06-04
7\quartus_prj\db\ex_spi.db_info 140 2015-05-16
7\quartus_prj\db\ex_spi.ipinfo 163 2015-05-16
7\quartus_prj\db\ex_spi.sld_design_entry.sci 277 2015-05-16
7\quartus_prj\ex_spi.qpf 1269 2015-05-12
7\quartus_prj\ex_spi.qsf 2582 2015-05-16
7\quartus_prj\ex_spi.qws 48 2015-05-16
7\quartus_prj\ipcore_dir\greybox_tmp\cbx_args.txt 400 2015-05-16
7\quartus_prj\ipcore_dir\ram_16x32_sr.mif 1849 2015-05-16
7\quartus_prj\ipcore_dir\ram_16x32_sr.qip 200 2015-05-16
7\quartus_prj\ipcore_dir\ram_16x32_sr.v 7350 2015-05-16
7\sim\altera_lib\altera_mf.v 2296569 2013-10-25
7\sim\dac_ini_16x32.mif 576 2012-07-29
7\sim\ex_spi.cr.mti 2 2020-09-17
7\sim\ex_spi.mpf 84819 2020-09-16
7\sim\ram_16x32_sr.mif 1849 2015-05-16
7\sim\ram_16x32_sr.ver 336 2020-09-16
7\sim\run.do 291 2015-05-16
7\sim\tb_ex_spi.v 1055 2015-05-16
7\sim\vsim.wlf 49152 2020-09-16
7\sim\work\@_opt\_lib.qdb 49152 2015-05-16
7\sim\work\@_opt\_lib.qdx 294 2015-05-16
7\sim\work\@_opt\_lib1_0.qdb 32768 2015-05-16
7\sim\work\@_opt\_lib1_0.qpg 259230 2015-05-16
7\sim\work\@_opt\_lib2_0.qdb 32768 2015-05-16
7\sim\work\@_opt\_lib2_0.qdx 1140 2015-05-16
7\sim\work\@_opt\_lib2_0.qpg 2278356 2015-05-16
7\sim\work\@_opt\_lib3_0.qdb 32768 2015-05-16
7\sim\work\@_opt\_lib3_0.qdx 294 2015-05-16
7\sim\work\@_opt\_lib3_0.qpg 181689 2015-05-16
7\sim\work\@_opt1\_lib.qdb 49152 2020-09-15
7\sim\work\@_opt1\_lib1_0.qdb 32768 2020-09-15
7\sim\work\@_opt1\_lib1_0.qpg 80209 2020-09-15
7\sim\work\@_opt1\_lib2_0.qdb 32768 2020-09-15
7\sim\work\@_opt1\_lib2_0.qpg 197999 2020-09-15
7\sim\work\@_opt1\_lib3_0.qdb 32768 2020-09-15
7\sim\work\@_opt1\_lib3_0.qpg 83129 2020-09-15
7\sim\work\@_opt1\_lib4_0.qdb 32768 2020-09-15
7\sim\work\@_opt1\_lib4_0.qpg 1820583 2020-09-15
7\sim\work\_info 14714 2020-09-16
7\sim\work\_lib.qdb 65536 2020-09-16
7\sim\work\_lib1_9.qdb 32768 2020-09-16
7\sim\work\_lib1_9.qpg 6522126 2020-09-16
7\sim\work\_vmake 29 2020-09-16
7\quartus_prj\ipcore_dir\greybox_tmp 0 2015-05-12
7\sim\work\@_opt 0 2015-05-16
7\sim\work\@_opt1 0 2020-09-15
7\sim\work\_temp 0 2020-09-15
7\sim\work\_tempmsg 0 2020-09-15
7\quartus_prj\db 0 2015-05-16
7\quartus_prj\ipcore_dir 0 2015-05-16
7\sim\altera_lib 0 2015-05-16
7\sim\work 0 2020-09-16
7\design 0 2015-05-12
7\documents 0 2015-05-12
7\quartus_prj 0 2015-05-16
7\sim 0 2020-09-17
7 0 2020-09-15
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