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sdram 仿真模型

Introduction - If you have any usage issues, please Google them yourself
sdram仿真模型参考设计,该设计可以直接对其读写操作,将数据存储至特定区域,然后读取,仿真结果正确
Packet file list
(Preview for download)
Packet : 107215787DDR3-SDRAM-Verilog-Model.zip filelist
1024Mb_ddr3_parameters.vh
2048Mb_ddr3_parameters.vh
4096Mb_ddr3_parameters.vh
8192Mb_ddr3_parameters.vh
ddr3.v
ddr3_dimm.v
ddr3_mcp.v
ddr3_module.v
readme.txt
subtest.vh
tb.v
Related instructions
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