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AES加密的VHDL源码

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2010-11-24
  • Size : 9.88kb
  • Downloaded :2次
  • Author :zhaojing.w@gmail.com
  • About : AES算法
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Introduction - If you have any usage issues, please Google them yourself
用VHDL语言实现的AES加密算法的源代码,已经在硬件上下载运行实现了。
Packet file list
(Preview for download)
Packet : AES.rar filelist
AES\addroundkey.vhd
AES\aes.vhd
AES\array.vhd
AES\bytesub.vhd
AES\keyextend.vhd
AES\mixcolumn.vhd
AES\ram_1.vhd
AES\shiftrow.vhd
AES\sub_array.vhd
AES
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