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串口verilog源代码

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2011-03-14
  • Size : 62.7kb
  • Downloaded :0次
  • Author :huangjiajun1213
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
串口UARTverilog源代码。包括控制模块、收、发模块。程序全,功能简洁,包含Q2工程
Packet file list
(Preview for download)
Packet : UART.rar filelist
UART\ClkUnit.v
UART\clk_1_wave0.jpg
UART\clk_pll.v
UART\clk_pll_bb.v
UART\clk_pll_wave0.jpg
UART\control_UART.v
UART\miniUART.v
UART\Rx_Unit.v
UART\test_uart.v
UART\Tx_Unit.v
UART\UART.v
UART
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