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h264 Verilog

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2011-03-17
  • Size : 808.37kb
  • Downloaded :2次
  • Author :kunchen87@yahoo.com.cn
  • About : Nobody
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h264 Verilog,用fpga实现基本档次功能。
Packet file list
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Packet : H.264.rar filelist
H.264\Beha_BitStream_ram.v
H.264\BitStream_buffer.v
H.264\BitStream_controller.v
H.264\bitstream_gclk_gen.v
H.264\BitStream_parser_FSM_gating.v
H.264\bs_decoding.v
H.264\cavlc_consumed_bits_decoding.v
H.264\cavlc_decoder.v
H.264\CodedBlockPattern_decoding.v
H.264\dependent_variable_decoding.v
H.264\DF_mem_ctrl.v
H.264\DF_pipeline.v
H.264\DF_reg_ctrl.v
H.264\DF_top.v
H.264\end_of_blk_decoding.v
H.264\exp_golomb_decoding.v
H.264\ext_frame_RAM0_wrapper.v
H.264\ext_frame_RAM1_wrapper.v
H.264\ext_RAM_ctrl.v
H.264\H.264.cr.mti
H.264\H.264.mpf
H.264\heading_one_detector.v
H.264\hybrid_pipeline_ctrl.v
H.264\Inter_mv_decoding.v
H.264\Inter_pred_CPE.v
H.264\Inter_pred_LPE.v
H.264\Inter_pred_pipeline.v
H.264\Inter_pred_reg_ctrl.v
H.264\Inter_pred_sliding_window.v
H.264\Inter_pred_top.v
H.264\Intra4x4_PredMode_decoding.v
H.264\Intra_pred_PE.v
H.264\Intra_pred_pipeline.v
H.264\Intra_pred_reg_ctrl.v
H.264\Intra_pred_top.v
H.264\IQIT.v
H.264\level_decoding.v
H.264\nC_decoding.v
H.264\nova.v
H.264\nova_defines.v
H.264\nova_tb.v
H.264\NumCoeffTrailingOnes_decoding.v
H.264\pc_decoding.v
H.264\QP_decoding.v
H.264\ram_async_1r_sync_1w.v
H.264\ram_sync_1r_sync_1w.v
H.264\reconstruction.v
H.264\rec_DF_RAM0_96x32.v
H.264\rec_DF_RAM0_wrapper.v
H.264\rec_DF_RAM1_96x32.v
H.264\rec_DF_RAM1_wrapper.v
H.264\rec_DF_RAM_ctrl.v
H.264\rec_gclk_gen.v
H.264\rev_1\Intra_pred_PE.areasrr
H.264\rev_1\Intra_pred_PE.edn
H.264\rev_1\Intra_pred_PE.fse
H.264\rev_1\Intra_pred_PE.sdf
H.264\rev_1\Intra_pred_PE.srd
H.264\rev_1\Intra_pred_PE.srm
H.264\rev_1\Intra_pred_PE.srr
H.264\rev_1\Intra_pred_PE.srs
H.264\rev_1\Intra_pred_PE.tlg
H.264\rev_1\Intra_pred_PE_sdc.sdc
H.264\rev_1\syntmp\Intra_pred_PE.msg
H.264\rev_1\syntmp\Intra_pred_PE.plg
H.264\run_decoding.v
H.264\sum.v
H.264\syntax_decoding.v
H.264\timescale.v
H.264\total_zeros_decoding.v
H.264\vsim.wlf
H.264\work\@inter_pred_reg_ctrl\_primary.dat
H.264\work\@inter_pred_reg_ctrl\_primary.vhd
H.264\work\@intra4x4_@pred@mode_decoding\verilog.asm
H.264\work\@intra4x4_@pred@mode_decoding\_primary.dat
H.264\work\@intra4x4_@pred@mode_decoding\_primary.vhd
H.264\work\@intra_pred_@p@e\verilog.asm
H.264\work\@intra_pred_@p@e\_primary.dat
H.264\work\@intra_pred_@p@e\_primary.vhd
H.264\work\@intra_pred_pipeline\_primary.dat
H.264\work\@intra_pred_pipeline\_primary.vhd
H.264\work\@intra_pred_reg_ctrl\_primary.dat
H.264\work\@intra_pred_reg_ctrl\_primary.vhd
H.264\work\@intra_pred_top\verilog.asm
H.264\work\@intra_pred_top\_primary.dat
H.264\work\@intra_pred_top\_primary.vhd
H.264\work\@p@e\verilog.asm
H.264\work\@p@e\_primary.dat
H.264\work\@p@e\_primary.vhd
H.264\work\main_seed_precomputation\_primary.dat
H.264\work\main_seed_precomputation\_primary.vhd
H.264\work\plane_@h@v_precomputation\_primary.dat
H.264\work\plane_@h@v_precomputation\_primary.vhd
H.264\work\plane_a_precomputation\_primary.dat
H.264\work\plane_a_precomputation\_primary.vhd
H.264\work\plane_bc_precomputation\_primary.dat
H.264\work\plane_bc_precomputation\_primary.vhd
H.264\work\ram_sync_1r_sync_1w\_primary.dat
H.264\work\ram_sync_1r_sync_1w\_primary.vhd
H.264\work\_info
H.264\rev_1\syntmp
H.264\work\@inter_pred_reg_ctrl
H.264\work\@intra4x4_@pred@mode_decoding
H.264\work\@intra_pred_@p@e
H.264\work\@intra_pred_pipeline
H.264\work\@intra_pred_reg_ctrl
H.264\work\@intra_pred_top
H.264\work\@p@e
H.264\work\main_seed_precomputation
H.264\work\plane_@h@v_precomputation
H.264\work\plane_a_precomputation
H.264\work\plane_bc_precomputation
H.264\work\ram_sync_1r_sync_1w
H.264\work\_temp
H.264\rev_1
H.264\work
H.264
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