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Title: 用FPGA实现DDS信号发生及用MODELSIM仿真 Download
 Description: 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
 Downloaders recently: [More information of uploader zhengguo22]
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