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基于FPGA的简易CPU程序

  • Category : VHDL-FPGA-Verilog
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  • Update : 2011-04-15
  • Size : 2.82mb
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  • Author :ztzbs00
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基于FPGA的简易CPU程序,可完成连乘或连加等程序
Packet file list
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Packet : mycpu.rar filelist
mycpu\ACC_ALU.bsf
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mycpu\db\altsyncram_3gu.tdf
mycpu\db\altsyncram_4041.tdf
mycpu\db\altsyncram_5gc1.tdf
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mycpu\db\altsyncram_qqv.tdf
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mycpu\db\altsyncram_stu.tdf
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mycpu\db\mycpu.fnsim.cdb
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mycpu\db\mycpu.signalprobe.cdb
mycpu\db\mycpu.sim.cvwf
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mycpu\db\mycpu.sld_design_entry.sci
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mycpu\db\mycpu.syn_hier_info
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mycpu\db\mycpu.tis_db_list.ddb
mycpu\db\mycpu0.rtl.mif
mycpu\db\mySequencing_Logic0.rtl.mif
mycpu\db\prev_cmp_mycpu.asm.qmsg
mycpu\db\prev_cmp_mycpu.fit.qmsg
mycpu\db\prev_cmp_mycpu.map.qmsg
mycpu\db\prev_cmp_mycpu.qmsg
mycpu\db\prev_cmp_mycpu.sim.qmsg
mycpu\db\prev_cmp_mycpu.tan.qmsg
mycpu\db\testcontrol0.rtl.mif
mycpu\db\tesy0.rtl.mif
mycpu\db\wed.wsf
mycpu\fzdy.bdf
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mycpu\jc.bsf
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mycpu\ljmyram.hex
mycpu\Logic.bsf
mycpu\Logic.vhd
mycpu\Logic.vhd.bak
mycpu\ls.
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