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- 源码下载
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[VHDL]
[源码]
- File Size:
- 374.68kb
- Update:
- 2011-05-27
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- Uploaded by:
- sakajj
Description: verilog全数字锁相环,用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
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