一个 Free 的 ARM-7 Core,是使用 Verilog 编成,综合后占用资源小,可以执行 uClinux 等程序或系统,内附详细说明的 PDF 档及源码 Verilog 编程等.

Packet : FreeARM7.rar filelist
arm
arm/arm.v
arm6
arm6/arm6.v
arm9verilog
arm9verilog/arm9_fpga2_verilog
arm9verilog/arm9_fpga2_verilog/align.v
arm9verilog/arm9_fpga2_verilog/alu.v
arm9verilog/arm9_fpga2_verilog/arm9.v
arm9verilog/arm9_fpga2_verilog/clock_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/clock_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/comp42_2.v
arm9verilog/arm9_fpga2_verilog/comp42_n40.v
arm9verilog/arm9_fpga2_verilog/comp42_n64.v
arm9verilog/arm9_fpga2_verilog/control.v
arm9verilog/arm9_fpga2_verilog/counters.v
arm9verilog/arm9_fpga2_verilog/dcache.v
arm9verilog/arm9_fpga2_verilog/decode.v
arm9verilog/arm9_fpga2_verilog/dtag.v
arm9verilog/arm9_fpga2_verilog/dtag_synth.v
arm9verilog/arm9_fpga2_verilog/ex.v
arm9verilog/arm9_fpga2_verilog/host.vhd
arm9verilog/arm9_fpga2_verilog/host_dcomp.vhd
arm9verilog/arm9_fpga2_verilog/host_icomp.vhd
arm9verilog/arm9_fpga2_verilog/icache.v
arm9verilog/arm9_fpga2_verilog/id.v
arm9verilog/arm9_fpga2_verilog/ifetch.v
arm9verilog/arm9_fpga2_verilog/interlock.v
arm9verilog/arm9_fpga2_verilog/io_conn_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/itag.v
arm9verilog/arm9_fpga2_verilog/itag_synth.v
arm9verilog/arm9_fpga2_verilog/lad_bus_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/lad_bus_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/lec25dscc25.v
arm9verilog/arm9_fpga2_verilog/led_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/led_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/mainmem.v
arm9verilog/arm9_fpga2_verilog/mapreg.v
arm9verilog/arm9_fpga2_verilog/mapspsr.v
arm9verilog/arm9_fpga2_verilog/me.v
arm9verilog/arm9_fpga2_verilog/mem_copy.c
arm9verilog/arm9_fpga2_verilog/mem_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/mem_init.dat
arm9verilog/arm9_fpga2_verilog/mem_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/mezz_mem_card_cfg.vhd
arm9verilog/arm9_fpga2_verilog/miniram.v
arm9verilog/arm9_fpga2_verilog/mmu_new.v
arm9verilog/arm9_fpga2_verilog/modelsim.ini
arm9verilog/arm9_fpga2_verilog/mult.v
arm9verilog/arm9_fpga2_verilog/multacc.v
arm9verilog/arm9_fpga2_verilog/pardef
arm9verilog/arm9_fpga2_verilog/pardef.v
arm9verilog/arm9_fpga2_verilog/pe0_bus_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pe0_bus_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pex.fes
arm9verilog/arm9_fpga2_verilog/pex.ucf
arm9verilog/arm9_fpga2_verilog/pex.vhd
arm9verilog/arm9_fpga2_verilog/pex_ent.vhd
arm9verilog/arm9_fpga2_verilog/pex_mezz_mem_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pex_mezz_mem_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pex_synth.vhd
arm9verilog/arm9_fpga2_verilog/pe_arm2mem_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pe_lad2mem_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/pe_mezz_mem_pkg.vhd
arm9verilog/arm9_fpga2_verilog/pe_pkg.vhd
arm9verilog/arm9_fpga2_verilog/pipe.v
arm9verilog/arm9_fpga2_verilog/ppselect.v
arm9verilog/arm9_fpga2_verilog/project_vcom.do
arm9verilog/arm9_fpga2_verilog/project_vsim.do
arm9verilog/arm9_fpga2_verilog/ram1p.v
arm9verilog/arm9_fpga2_verilog/ram1p_synth.v
arm9verilog/arm9_fpga2_verilog/ram2p.v
arm9verilog/arm9_fpga2_verilog/ram2p_synth.v
arm9verilog/arm9_fpga2_verilog/README
arm9verilog/arm9_fpga2_verilog/regfile.v
arm9verilog/arm9_fpga2_verilog/shifter.v
arm9verilog/arm9_fpga2_verilog/system_cfg.vhd
arm9verilog/arm9_fpga2_verilog/systolic_if_entarch.vhd
arm9verilog/arm9_fpga2_verilog/systolic_io_entarch.vhd
arm9verilog/arm9_fpga2_verilog/tag.v
arm9verilog/arm9_fpga2_verilog/testarm.vhx
arm9verilog/arm9_fpga2_verilog/vlog.opt
arm9verilog/arm9_fpga2_verilog/wave.do
arm9verilog/arm9_fpga2_verilog/xilinx_pkg.vhd
uclinux
uclinux/arm6.v
uclinux/boot0.bin
uclinux/tb_sp.v
uclinux/uclinux0.bin
uclinux1
uclinux1/boot1.bin
uclinux1/uclinux1.bin
uclinux2
uclinux2/boot2.bin
uclinux2/uclinux2.bin
v0
v0/anotherone
v0/anotherone/boot0.rom
v0/anotherone/skyeye.conf
v0/anotherone/uclinux0
v1
v1/boot1.rom
v1/skyeye.conf
v1/uclinux1
v2
v2/v0.2
v2/v0.2/boot.rom
v2/v0.2/skyeye.conf
v2/v0.2/uclinux
arm_proj.pdf
FreeARM7_intro.pdf

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