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Code_for_Bilinear Interpolation

  • Category : VHDL-FPGA-Verilog
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  • Update : 2011-12-26
  • Size : 489.26kb
  • Downloaded :1次
  • Author :pili0211
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
根據不同測試pattern,設計的電路要能對16×16 pixels的原圖影像作縮放,產生16×16、32×32的放大或縮小影像。
Packet file list
(Preview for download)
Packet : verilog_Bilinear Interpolation.rar filelist
verilog_Bilinear Interpolation/post-sim/scale.v
verilog_Bilinear Interpolation/post-sim/scale_tb.v
verilog_Bilinear Interpolation/post-sim/scale_v.sdo
verilog_Bilinear Interpolation/pre-sim/scale.v
verilog_Bilinear Interpolation/pre-sim/scale_tb.v
verilog_Bilinear Interpolation/post-sim
verilog_Bilinear Interpolation/pre-sim
verilog_Bilinear Interpolation
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