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experiment4_play

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-01-11
  • Size : 190.57kb
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  • Author :testsb
  • About : 童长威
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VHDL实验四,设计一个异步清零和同步时钟使能的4位加法计数器-VHDL Experiment 4, an asynchronous reset and synchronous design clock enable 4-bit adder
Packet file list
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Packet : 95464062experiment4_play.rar filelist
experiment4_play/cmp_state.ini
experiment4_play/cnt10.asm.rpt
experiment4_play/cnt10.done
experiment4_play/cnt10.fit.eqn
experiment4_play/cnt10.fit.rpt
experiment4_play/cnt10.fit.smsg
experiment4_play/cnt10.fit.summary
experiment4_play/cnt10.flow.rpt
experiment4_play/cnt10.jpg
experiment4_play/cnt10.map.eqn
experiment4_play/cnt10.map.rpt
experiment4_play/cnt10.map.summary
experiment4_play/cnt10.pin
experiment4_play/cnt10.pof
experiment4_play/cnt10.qpf
experiment4_play/cnt10.qsf
experiment4_play/cnt10.qws
experiment4_play/cnt10.sim.rpt
experiment4_play/cnt10.sof
experiment4_play/cnt10.tan.rpt
experiment4_play/cnt10.tan.summary
experiment4_play/cnt10.vhd
experiment4_play/cnt10.vwf
experiment4_play/cnt10_assignment_defaults.qdf
experiment4_play/cnt10.jpg.jpg
experiment4_play/db/cnt10.pre_map.hdb
experiment4_play/db/cnt10.sim.qmsg
experiment4_play/db/cnt10.rtlv_sg_swap.cdb
experiment4_play/db/cnt10.cmp.rdb
experiment4_play/db/cnt10.sim.vwf
experiment4_play/db/cnt10.map.qmsg
experiment4_play/db/cnt10.rtlv.hdb
experiment4_play/db/cnt10.sim.rdb
experiment4_play/db/cnt10.pre_map.cdb
experiment4_play/db/cnt10.map.logdb
experiment4_play/db/cnt10.rtlv_sg.cdb
experiment4_play/db/cnt10.sgdiff.hdb
experiment4_play/db/cnt10.fit.qmsg
experiment4_play/db/cnt10.map.cdb
experiment4_play/db/cnt10.map.hdb
experiment4_play/db/cnt10.cmp.logdb
experiment4_play/db/cnt10.sgdiff.cdb
experiment4_play/db/cnt10.sld_design_entry_dsc.sci
experiment4_play/db/cnt10.sld_design_entry.sci
experiment4_play/db/cnt10.signalprobe.cdb
experiment4_play/db/cnt10.rpp.qmsg
experiment4_play/db/cnt10.sgate.rvd
experiment4_play/db/cnt10.asm.qmsg
experiment4_play/db/cnt10.cmp.cdb
experiment4_play/db/cnt10.tan.qmsg
experiment4_play/db/cnt10.cmp0.ddb
experiment4_play/db/cnt10.sgate_sm.rvd
experiment4_play/db/cnt10_cmp.qrpt
experiment4_play/db/wed.zsf
experiment4_play/db/cnt10.db_info
experiment4_play/db/cnt10.sim.hdb
experiment4_play/db/cnt10.cbx.xml
experiment4_play/db/cnt10.hif
experiment4_play/db/cnt10.hier_info
experiment4_play/db/cnt10.psp
experiment4_play/db/cnt10.dbp
experiment4_play/db/cnt10.syn_hier_info
experiment4_play/db/cnt10.cmp.kpt
experiment4_play/db/cnt10.eds_overflow
experiment4_play/db/cnt10.(0).cnf.cdb
experiment4_play/db/cnt10.(0).cnf.hdb
experiment4_play/db/cnt10.cmp.hdb
experiment4_play/db/cnt10.cmp.tdb
experiment4_play/db/cnt10.eco.cdb
experiment4_play/db
experiment4_play
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