several VHDL source code, and in my preparation of a five pipelined RISC CPU code

靳远－源程序(处于综合方便的目的，本程序有些地方初始值是不同于原稿的，本程序仅供参考）
.....................................................................................\alu.vhd
.....................................................................................\control.vhd
.....................................................................................\coreofCPU.vhd
.....................................................................................\CPU.prd
.....................................................................................\CPU.prj
.....................................................................................\data_rom.vhd
.....................................................................................\ins_rom.vhd
.....................................................................................\mux2_1.vhd
.....................................................................................\mux4_1.vhd
.....................................................................................\opt.vhd
.....................................................................................\rev_1
.....................................................................................\.....\.recordref
.....................................................................................\.....\coreofCPU.edf
.....................................................................................\.....\coreofCPU.fse
.....................................................................................\.....\coreofCPU.ncf
.....................................................................................\.....\coreofCPU.plg
.....................................................................................\.....\coreofCPU.srd
.....................................................................................\.....\coreofCPU.srm
.....................................................................................\.....\coreofCPU.srr
.....................................................................................\.....\coreofCPU.srs
.....................................................................................\.....\coreofCPU.ta
.....................................................................................\.....\coreofCPU.taq
.....................................................................................\.....\coreofCPU.tlg
.....................................................................................\.....\coreofCPU.zip
.....................................................................................\.....\coreofCPU_ta.srm
.....................................................................................\.....\traplog.tlg
.....................................................................................\test_banch.vhd
.....................................................................................\transcript

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