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usb1.1_Verilog

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 128kb
  • Downloaded :1次
  • Author :李***
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Introduction - If you have any usage issues, please Google them yourself
USB1.1 IP core for device control, written with hardware describing language of Verilog.
Packet file list
(Preview for download)
usb1.1
......\generic_fifos
......\.............\generic_fifos
......\.............\.............\generic_fifos
......\.............\.............\.............\bench
......\.............\.............\.............\.....\CVS
......\.............\.............\.............\.....\...\Entries
......\.............\.............\.............\.....\...\Repository
......\.............\.............\.............\.....\...\Root
......\.............\.............\.............\.....\verilog
......\.............\.............\.............\.....\.......\CVS
......\.............\.............\.............\.....\.......\...\Entries
......\.............\.............\.............\.....\.......\...\Repository
......\.............\.............\.............\.....\.......\...\Root
......\.............\.............\.............\.....\.......\test_bench_top.v
......\.............\.............\.............\CVS
......\.............\.............\.............\...\Entries
......\.............\.............\.............\...\Repository
......\.............\.............\.............\...\Root
......\.............\.............\.............\doc
......\.............\.............\.............\...\CVS
......\.............\.............\.............\...\...\Entries
......\.............\.............\.............\...\...\Repository
......\.............\.............\.............\...\...\Root
......\.............\.............\.............\...\README.txt
......\.............\.............\.............\rtl
......\.............\.............\.............\...\CVS
......\.............\.............\.............\...\...\Entries
......\.............\.............\.............\...\...\Repository
......\.............\.............\.............\...\...\Root
......\.............\.............\.............\...\verilog
......\.............\.............\.............\...\.......\CVS
......\.............\.............\.............\...\.......\...\Entries
......\.............\.............\.............\...\.......\...\Repository
......\.............\.............\.............\...\.......\...\Root
......\.............\.............\.............\...\.......\generic_fifo_dc.v
......\.............\.............\.............\...\.......\generic_fifo_dc_gray.v
......\.............\.............\.............\...\.......\generic_fifo_lfsr.v
......\.............\.............\.............\...\.......\generic_fifo_sc_a.v
......\.............\.............\.............\...\.......\generic_fifo_sc_b.v
......\.............\.............\.............\...\.......\lfsr.v
......\.............\.............\.............\...\.......\timescale.v
......\.............\.............\.............\sim
......\.............\.............\.............\...\CVS
......\.............\.............\.............\...\...\Entries
......\.............\.............\.............\...\...\Repository
......\.............\.............\.............\...\...\Root
......\.............\.............\.............\...\rtl_sim
......\.............\.............\.............\...\.......\bin
......\.............\.............\.............\...\.......\...\CVS
......\.............\.............\.............\...\.......\...\...\Entries
......\.............\.............\.............\...\.......\...\...\Repository
......\.............\.............\.............\...\.......\...\...\Root
......\.............\.............\.............\...\.......\...\Makefile
......\.............\.............\.............\...\.......\CVS
......\.............\.............\.............\...\.......\...\Entries
......\.............\.............\.............\...\.......\...\Repository
......\.............\.............\.............\...\.......\...\Root
......\.............\.............\.............\...\.......\run
......\.............\.............\.............\...\.......\...\CVS
......\.............\.............\.............\...\.......\...\...\Entries
......\.............\.............\.............\...\.......\...\...\Repository
......\.............\.............\.............\...
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