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9.16fifoasi

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 2.63mb
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  • Author :yjb_****
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Introduction - If you have any usage issues, please Google them yourself
the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Packet file list
(Preview for download)
9.16fifoasi
...........\16to8ddf.bdf
...........\16to8ddf.bsf
...........\16to8vir.v
...........\16to8vri.v
...........\8to16ddf.bdf
...........\8to16ddf.bsf
...........\altddio_bidir0.bsf
...........\altddio_bidir0.v
...........\altddio_bidir0_bb.v
...........\altpll0.bsf
...........\altpll0.tdf
...........\altpll1.bsf
...........\altpll1.v
...........\altpll1_bb.v
...........\altshift_taps0.v
...........\altshift_taps0_bb.v
...........\asitodsp.bsf
...........\asitodsp.v
...........\asitodsp_bb.v

...........\asitodsp_waveforms.html
...........\cmp_state.ini
...........\control.v
...........\db
...........\..\add_sub_fub.tdf
...........\..\altsyncram_bv01.tdf
...........\..\alt_synch_pipe_2a3.tdf
...........\..\a_gray2bin_p4b.tdf
...........\..\a_graycounter_i06.tdf
...........\..\cntr_5c7.tdf
...........\..\cntr_uu7.tdf
...........\..\dcfifo_dv21.tdf
...........\..\dffpipe_2a3.tdf
...........\..\fifoasi.asm.qmsg
...........\..\fifoasi.atom.rvd
...........\..\fifoasi.cmp.cdb
...........\..\fifoasi.cmp.ddb
...........\..\fifoasi.cmp.hdb
...........\..\fifoasi.cmp.rdb
...........\..\fifoasi.cmp.tdb
...........\..\fifoasi.dat_manager.dat
...........\..\fifoasi.db_info
...........\..\fifoasi.fit.qmsg
...........\..\fifoasi.hier_info
...........\..\fifoasi.hif
...........\..\fifoasi.icc
...........\..\fifoasi.map.cdb
...........\..\fifoasi.map.hdb
...........\..\fifoasi.map.qmsg
...........\..\fifoasi.pre_map.hdb
...........\..\fifoasi.project.hdb
...........\..\fifoasi.rpp.qmsg
...........\..\fifoasi.rtlv.hdb
...........\..\fifoasi.rtlv_sg.cdb
...........\..\fifoasi.rtlv_sg_swap.cdb
...........\..\fifoasi.sgate.rvd
...........\..\fifoasi.sgdiff.cdb
...........\..\fifoasi.sgdiff.hdb
...........\..\fifoasi.signalprobe.cdb
...........\..\fifoasi.sim.hdb
...........\..\fifoasi.sim.qmsg
...........\..\fifoasi.sim.rdb
...........\..\fifoasi.sld_design_entry.sci
...........\..\fifoasi.sld_design_entry_dsc.sci
...........\..\fifoasi.syn_hier_info
...........\..\fifoasi.tan.qmsg
...........\..\fifoasi_cmp.qrpt
...........\..\fifoasi_sim.qrpt
...........\..\mux_pgc.tdf
...........\dsptoasi.bsf
...........\dsptoasi.v
...........\dsptoasi_bb.v

...........\dsptoasi_waveforms.html
...........\fifoasi.asm.rpt
...........\fifoasi.done
...........\fifoasi.fit.eqn
...........\fifoasi.fit.rpt
...........\fifoasi.fit.summary
...........\fifoasi.flow.rpt
...........\fifoasi.map.eqn
...........\fifoasi.map.rpt
...........\fifoasi.map.summary
...........\fifoasi.pin
...........\fifoasi.pof
...........\fifoasi.qpf
...........\fifoasi.qsf
...........\fifoasi.qws
...........\fifoasi.sim.rpt
...........\fifoasi.sof
...........\fifoasi.tan.rpt
...........\fifoasi.tan.summary
...........\fifoasi.tcl
...........\fifoasi_pwr_cal.txt
...........\fifo_asi.bdf
...........\INT.v
...........\lpm_bustri0.bsf
...........\lpm_bustri0.v
...........\lpm_bustri0_bb.v
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