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source7-8

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 8kb
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Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8
Packet file list
(Preview for download)
chap7
.....\add4_1.v
.....\add4_2.v
.....\add4_3.v
.....\count4.v
.....\full_add1.v
.....\full_add2.v
.....\full_add3.v
.....\full_add4.v
.....\full_add5.v
.....\half_add1.v
.....\half_add2.v
.....\half_add3.v
.....\half_add4.v
.....\mux2_1a.v
.....\mux2_1b.v
.....\mux2_1c.v
.....\mux4_1a.v
.....\mux4_1b.v
.....\mux4_1c.v
.....\mux4_1d.v
chap8
.....\add8_tp.v
.....\carry_udp.v
.....\carry_udpx1.v
.....\carry_udpx2.v
.....\count8_tp.v
.....\delay.v
.....\dff.v
.....\dff_udp.v
.....\latch.v
.....\mult_tp.v
.....\mux31.v
.....\mux_tp.v
.....\random_tp.v
.....\rom.v
.....\test1.v
.....\test2.v
.....\time_dif.v
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