This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.

test
....\cpu_admux.v
....\cpu_alu.v
....\cpu_clkg.v
....\cpu_datactrl.v
....\cpu_mem.v
....\cpu_pcounter.v
....\cpu_register.v
....\cpu_sctrl.v
....\cpu_top.v
....\test.cr.mti
....\test.mpf
....\transcript
....\vsim.wlf
....\work
....\....\@f@i@r@filter_1
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\cpu_admux
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_alu
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_clkg
....\....\........\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\cpu_datactrl
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_mem
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_pcounter
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_register
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_sctrl
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_top
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\my@test
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\_info

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