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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 134kb
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  • Author :刘***
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Introduction - If you have any usage issues, please Google them yourself
VHDL 0~
Packet file list
(Preview for download)
plj
...\cmp_state.ini
...\control.bsf
...\control.vhd
...\control.vwf
...\count24.acf
...\count24.hif
...\count24.vhd
...\count60.acf
...\count60.hif
...\count60.vhd
...\count8.vhd
...\counter10.bsf
...\counter10.vhd
...\db
...\..\cntr_ge8.tdf
...\..\frequ.asm.qmsg
...\..\frequ.cmp.cdb
...\..\frequ.cmp.ddb
...\..\frequ.cmp.hdb
...\..\frequ.cmp.rdb
...\..\frequ.cmp.tdb
...\..\frequ.cmp0.ddb
...\..\frequ.db_info
...\..\frequ.eco.cdb
...\..\frequ.eds_overflow
...\..\frequ.fit.qmsg
...\..\frequ.hier_info
...\..\frequ.hif
...\..\frequ.map.cdb
...\..\frequ.map.hdb
...\..\frequ.map.qmsg
...\..\frequ.pre_map.cdb
...\..\frequ.pre_map.hdb
...\..\frequ.psp
...\..\frequ.rtlv.hdb
...\..\frequ.rtlv_sg.cdb
...\..\frequ.rtlv_sg_swap.cdb
...\..\frequ.sgdiff.cdb
...\..\frequ.sgdiff.hdb
...\..\frequ.sim.hdb
...\..\frequ.sim.qmsg
...\..\frequ.sim.rdb
...\..\frequ.sim.vwf
...\..\frequ.sld_design_entry.sci
...\..\frequ.sld_design_entry_dsc.sci
...\..\frequ.syn_hier_info
...\..\frequ.tan.qmsg
...\..\frequ_cmp.qrpt
...\..\frequ_sim.qrpt
...\display.bsf
...\display.vhd
...\display2.bsf
...\display2.vhd
...\frequ.asm.rpt
...\frequ.bdf
...\frequ.bsf
...\frequ.done
...\frequ.fit.eqn
...\frequ.fit.rpt
...\frequ.fit.summary
...\frequ.flow.rpt
...\frequ.map.eqn
...\frequ.map.rpt
...\frequ.map.summary
...\frequ.pin
...\frequ.pof
...\frequ.qpf
...\frequ.qsf
...\frequ.qws
...\frequ.sim.rpt
...\frequ.sof
...\frequ.tan.rpt
...\frequ.tan.summary
...\frequ.vwf
...\frequ_assignment_defaults.qdf
...\f_dis.vhd
...\led7.bdf
...\mux2.acf
...\mux2.hif
...\mux2.vhd
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