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vhdl_LED

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 326kb
  • Downloaded :0次
  • Author :刘***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
lattice experimental use of the use of sample modules : clock source modules, dot-matrix display module, pulse along the module. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connecting lines and procedures for loading 4. Pulse module along the MS1 to reset button, reset button, when the lights were effective, Lattice pieces will be shown on Chinese characters.
Packet file list
(Preview for download)
LED
...\display.acf
...\display.fit
...\display.hex
...\display.hif
...\display.mmf
...\display.ndb
...\display.pin
...\display.pof
...\display.rpt
...\display.snf
...\display.sof
...\DISPLAY.sym
...\display.ttf
...\display.vhd
...\led.acf
...\led.fit
...\led.gdf
...\led.hex
...\led.hif
...\led.mmf
...\led.ndb
...\led.pin
...\led.pof
...\led.rpt
...\led.scf
...\led.snf
...\led.sof
...\led.ttf
...\led.txt
...\LIB.DLS
...\rom.acf
...\rom.hif
...\rom.mif
...\U0170215.DLS
...\U3493642.DLS
...\U4910123.DLS
...\汉字提取软件.exe
...\点阵显示实验示例使用说明.doc
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