CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.

cpld_bus
........\bus_ISM.bsf
........\bus_ISM.v
........\cmp_state.ini
........\cpld_bus.asm.rpt
........\cpld_bus.bdf
........\cpld_bus.done
........\cpld_bus.dse.rpt
........\cpld_bus.fit.eqn
........\cpld_bus.fit.rpt
........\cpld_bus.fit.summary
........\cpld_bus.flow.rpt
........\cpld_bus.map.eqn
........\cpld_bus.map.rpt
........\cpld_bus.map.summary
........\cpld_bus.pin
........\cpld_bus.pof
........\cpld_bus.qpf
........\cpld_bus.qsf
........\cpld_bus.qws
........\cpld_bus.sim.rpt
........\cpld_bus.sof
........\cpld_bus.tan.rpt
........\cpld_bus.tan.summary
........\cpld_bus.vwf
........\Data_Out_Mux.bsf
........\data_out_mux.v
........\db
........\..\cpld_bus.asm.qmsg
........\..\cpld_bus.cmp.cdb
........\..\cpld_bus.cmp.ddb
........\..\cpld_bus.cmp.hdb
........\..\cpld_bus.cmp.rdb
........\..\cpld_bus.cmp.tdb
........\..\cpld_bus.cmp0.ddb
........\..\cpld_bus.db_info
........\..\cpld_bus.eco.cdb
........\..\cpld_bus.eds_overflow
........\..\cpld_bus.fit.qmsg
........\..\cpld_bus.hier_info
........\..\cpld_bus.hif
........\..\cpld_bus.icc
........\..\cpld_bus.map.cdb
........\..\cpld_bus.map.hdb
........\..\cpld_bus.map.qmsg
........\..\cpld_bus.pre_map.cdb
........\..\cpld_bus.pre_map.hdb
........\..\cpld_bus.psp
........\..\cpld_bus.rtlv.hdb
........\..\cpld_bus.rtlv_sg.cdb
........\..\cpld_bus.rtlv_sg_swap.cdb
........\..\cpld_bus.sgdiff.cdb
........\..\cpld_bus.sgdiff.hdb
........\..\cpld_bus.sim.hdb
........\..\cpld_bus.sim.qmsg
........\..\cpld_bus.sim.rdb
........\..\cpld_bus.sld_design_entry.sci
........\..\cpld_bus.sld_design_entry_dsc.sci
........\..\cpld_bus.syn_hier_info
........\..\cpld_bus.tan.qmsg
........\..\cpld_bus_cmp.qrpt
........\..\cpld_bus_sim.qrpt
........\decode.bsf
........\decode.v
........\Output_reg.bsf
........\Output_reg.inc
........\Output_reg.v
........\quartus_map.out
........\test.bsf
........\undo_redo.txt

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