32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only

32位-33M 从模式(target)PCI接口参考设计_lattice
..............................................\32位-33M 从模式(target)PCI接口参考设计_lattice说明.pdf
..............................................\base_addr_chk.v
..............................................\config_mux.v
..............................................\glue.v
..............................................\pargen.v
..............................................\pci_top.v
..............................................\rd1008.pdf
..............................................\retry_count.v
..............................................\state_machine.v
..............................................\tstbench.zip

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