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key_control

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 139kb
  • Downloaded :0次
  • Author :分****
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4x4 electronic locks central control system. Six input control.
Packet file list
(Preview for download)
control
.......\cmp_state.ini
.......\control.asm.rpt
.......\control.done
.......\control.fit.eqn
.......\control.fit.rpt
.......\control.fit.summary
.......\control.flow.rpt
.......\control.map.eqn
.......\control.map.rpt
.......\control.map.summary
.......\control.pin
.......\control.pof
.......\control.qpf
.......\control.qsf
.......\control.qws
.......\control.sim.rpt
.......\control.sof
.......\control.tan.rpt
.......\control.tan.summary
.......\control.vhd
.......\control.vwf
.......\control_1.pof
.......\db
.......\..\control.asm.qmsg
.......\..\control.cmp.cdb
.......\..\control.cmp.ddb
.......\..\control.cmp.hdb
.......\..\control.cmp.rdb
.......\..\control.cmp.tdb
.......\..\control.db_info
.......\..\control.fit.qmsg
.......\..\control.hier_info
.......\..\control.hif
.......\..\control.map.cdb
.......\..\control.map.hdb
.......\..\control.map.qmsg
.......\..\control.pre_map.hdb
.......\..\control.project.hdb
.......\..\control.rtlv.hdb
.......\..\control.rtlv_sg.cdb
.......\..\control.rtlv_sg_swap.cdb
.......\..\control.sgdiff.cdb
.......\..\control.sgdiff.hdb
.......\..\control.sim.hdb
.......\..\control.sim.qmsg
.......\..\control.sim.rdb
.......\..\control.sim.vwf
.......\..\control.sld_design_entry.sci
.......\..\control.sld_design_entry_dsc.sci
.......\..\control.syn_hier_info
.......\..\control.tan.qmsg
.......\..\control_cmp.qrpt
.......\..\control_sim.qrpt
.......\serv_req_info.txt
.......\sim.cfg
control.vhd
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