design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch

hw3
...\0.mgf
...\1.mgf
...\3.mgf
...\bde.set
...\compile
...\.......\contents.lib~
...\.......\hw3.epr
...\.......\hw3.erf
...\.......\sources.sth
...\compile.cfg
...\elaboration.log
...\hw3.adf
...\hw3.LIB
...\hw3.wsp
...\log
...\...\console.log
...\projlib.cfg
...\src
...\...\hw3.vhd
...\...\stream.awf
...\...\test_stream.vhd

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