the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3

hw4
...\0.mgf
...\1.mgf
...\3.mgf
...\bde.set
...\compile
...\.......\contents.lib~
...\.......\hw4.epr
...\.......\hw4.erf
...\.......\sources.sth
...\compile.cfg
...\elaboration.log
...\hw4.adf
...\hw4.LIB
...\hw4.wsp
...\log
...\...\console.log
...\projlib.cfg
...\src
...\...\pcm.awf
...\...\pcm.vhd
...\...\test_pcm.vhd

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