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VHDL_100Examples

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 194kb
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  • Author :韩***
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Introduction - If you have any usage issues, please Google them yourself
Beijing University Institute of ASIC design hundred examples of VHDL Design
Packet file list
(Preview for download)
VHDL_100Examples
................\10_function
................\...........\10_bit_to_int.vhd
................\...........\README.TXT
................\11_wiredor
................\..........\11_wiredor.vhd
................\..........\README.TXT
................\12_convert
................\..........\12_convert.vhd
................\..........\README.TXT
................\13_SHL
................\......\13_SHL.VHD
................\......\README.TXT
................\14_MVL7_functions
................\.................\14_MVL7_functions.vhd
................\.................\README.TXT
................\15_MUX41
................\........\15_MUX41.VHD
................\........\15_MVL7_functions.vhd
................\........\15_MVL7_syn_types.vhd
................\........\15_test_vectors_mux41.vhd
................\........\15_TYPES.VHD
................\........\README.TXT
................\16_MUX
................\......\16_multiple_mux.vhd
................\......\16_MVL7_functions.vhd
................\......\16_test_vectors.vhd
................\......\16_TYPES.VHD
................\......\README.TXT
................\......\TYPES.VHD
................\17_parity
................\.........\17_parity.vhd
................\.........\17_test_bench.vhd
................\.........\README.TXT
................\18_LIB
................\......\18_tech_lib.vhd
................\......\18_test_lib.vhd
................\......\README.TXT
................\19_test_194
................\...........\19_test_194.vhd
................\1_ADDER
................\.......\1_ADDER.VHD
................\.......\README.TXT
................\20_test_159
................\...........\20_test_159.vhd
................\21_test_13a
................\...........\21_test_13a.vhd
................\22_deadlock
................\...........\22_deadlock.vhd
................\23_test_120
................\...........\23_Test_120.vhd
................\24_test_195
................\...........\24_test_195.vhd
................\25_test_1
................\.........\25_test_1.vhd
................\.........\25_test_1a.vhd
................\26_test_74s
................\...........\26_test_74s.vhd
................\27_test_16
................\..........\27_test_16.vhd
................\28_test_64a
................\...........\28_Test_64a.vhd
................\29_test_35
................\..........\29_Test_35.vhd
................\2_ADDER
................\.......\2_ADDER.VHD
................\.......\README.TXT
................\30_test_3
................\.........\30_Test_3.vhd
................\31_test_35b
................\...........\31_test_35b.vhd
................\32_test_110b
................\............\32_test_110b.vhd
................\33_comparer
................\...........\33_COMP.VHD
................\...........\33_comparer.vhd
................\...........\33_SIMU.VHD
................\...........\README.TXT
................\34_BUS
................\......\34_readwrite.VHD
................\......\34_readwrite_stim.vhd
................\......\README.TXT
................\35_486_bus
................\..........\35_486_bus.vhd
................\..........\35_486_sys.vhd
................\..........\35_bit_pack.vhd
................\..........\35_bus_test.vhd
................\..........\35_ram_controller.vhd
................\..........\75_RAM.VHD
................\..........\README.TXT
................\36_GCD
................\......\36_GCD.VHD
................\......\36_TEST.VHD
................\......\README.TXT
................\37_test_105
................\...........\37_test_105.vhd
................\38_test_28
................\..........\38_Test_28.vhd
................\39_wst0dp
................\.........\39_wst0dp.vhd
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