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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 192kb
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  • Author :雷***
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Introduction - If you have any usage issues, please Google them yourself
UART Universal Asynchronous Receiver and build environment for Quartus
Packet file list
(Preview for download)
uart2
.....\cmp_state.ini
.....\db
.....\..\test.asm.qmsg
.....\..\test.cbx.xml
.....\..\test.cmp.cdb
.....\..\test.cmp.hdb
.....\..\test.cmp.rdb
.....\..\test.cmp.tdb
.....\..\test.cmp0.ddb
.....\..\test.db_info
.....\..\test.eco.cdb
.....\..\test.eds_overflow
.....\..\test.fit.qmsg
.....\..\test.hier_info
.....\..\test.hif
.....\..\test.map.cdb
.....\..\test.map.hdb
.....\..\test.map.qmsg
.....\..\test.pre_map.cdb
.....\..\test.pre_map.hdb
.....\..\test.psp
.....\..\test.rtlv.hdb
.....\..\test.rtlv_sg.cdb
.....\..\test.rtlv_sg_swap.cdb
.....\..\test.sgdiff.cdb
.....\..\test.sgdiff.hdb
.....\..\test.sim.hdb
.....\..\test.sim.qmsg
.....\..\test.sim.rdb
.....\..\test.sld_design_entry.sci
.....\..\test.sld_design_entry_dsc.sci
.....\..\test.syn_hier_info
.....\..\test.tan.qmsg
.....\..\test_cmp.qrpt
.....\..\test_sim.qrpt
.....\test.asm.rpt
.....\test.bdf
.....\test.done
.....\test.fit.eqn
.....\test.fit.rpt
.....\test.fit.summary
.....\test.flow.rpt
.....\test.map.eqn
.....\test.map.rpt
.....\test.map.summary
.....\test.pin
.....\test.pof
.....\test.qpf
.....\test.qsf
.....\test.qws
.....\test.sim.rpt
.....\test.tan.rpt
.....\test.tan.summary
.....\test.vwf
.....\uart.bsf
.....\uart.v
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