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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 31kb
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  • Author :李***
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Introduction - If you have any usage issues, please Google them yourself
Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Packet file list
(Preview for download)
crc_16
......\crc.cr.mti
......\crc.mpf
......\crc_receive.v
......\crc_send.v
......\crc_test.v
......\vsim.wlf
......\work
......\....\crc_receive
......\....\...........\verilog.asm
......\....\...........\_primary.dat
......\....\...........\_primary.vhd
......\....\crc_send
......\....\........\verilog.asm
......\....\........\_primary.dat
......\....\........\_primary.vhd
......\....\crc_test
......\....\........\verilog.asm
......\....\........\_primary.dat
......\....\........\_primary.vhd
......\....\_info
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