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[eda]vhdl

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 217kb
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  • Author :林****
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Introduction - If you have any usage issues, please Google them yourself
Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Packet file list
(Preview for download)
1002016p_Sa
...........\1002016_EDA实验报告一.doc
...........\2endaddr.gdf

...........\addr.vhd
...........\endaddr.gdf
...........\halfaddr.vhd
1002016p_Sa_2
.............\000.The Electronic Design Automation (EDA)
.............\1002016_EDA实验报告二.doc
.............\light.vhd
.............\light_6.acf
.............\light_6.hif
.............\Light_6.vhd
1002016p_Sa_3
.............\1002016_EDA实验报告三.doc
.............\tosin.vhd
1002016p_Sa_4
.............\1002016_EDA实验报告四.doc
.............\CNT8.VHD
.............\DISPLAY.GDF
.............\LED.VHD
.............\MUX8.VHD
1002016p_Sa_5
.............\1002016_EDA实验报告五.doc
.............\cnt10.vhd
.............\CNT8.VHD
.............\king8.gdf
.............\LED.VHD
.............\MUX8.VHD
1002016p_Sa_6
.............\1002016_EDA实验报告六.doc
.............\cnt10.vhd
.............\CNT8.VHD
.............\CONTROL.VHD
.............\CONTROL.VHD MYREG.VHD 参考1002025
.............\king8.gdf
.............\LED.VHD
.............\MUX8.VHD
.............\MYREG.VHD
1002016p_Sa_clockHMS
....................\1002016_EDA实验报告七_CLOCK.doc
....................\cnt10.vhd
....................\cnt24.vhd
....................\cnt6.vhd
....................\CNT8.VHD
....................\king8.gdf
....................\LED.VHD
....................\MUX8.VHD
....................\this clock_18hH.60M.60S
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