video signal encoder, Verilog, to see whether the reference value?

全电视信号编码器_from_opencore
..............................\全电视信号编码器_from_opencore
..............................\..............................\Documentation
..............................\..............................\.............\DVE_CCIR_601_core.PDF
..............................\..............................\Simulation
..............................\..............................\..........\Verilog
..............................\..............................\..........\.......\dve_ccir_aps.v
..............................\..............................\..........\.......\dve_ccir_dds.v
..............................\..............................\..........\.......\dve_ccir_dph.v
..............................\..............................\..........\.......\dve_ccir_fir.v
..............................\..............................\..........\.......\dve_ccir_lut.v
..............................\..............................\..........\.......\dve_ccir_lut7b.v
..............................\..............................\..........\.......\dve_ccir_mlt.v
..............................\..............................\..........\.......\dve_ccir_mlt8x9.v
..............................\..............................\..........\.......\dve_ccir_TB.v
..............................\..............................\..........\.......\dve_ccir_top.v
..............................\..............................\..........\.......\dve_ccir_vtg.v
..............................\..............................\Synthesis
..............................\..............................\.........\High_performance
..............................\..............................\.........\................\Verilog
..............................\..............................\.........\................\.......\dve_ccir_aps.v
..............................\..............................\.........\................\.......\dve_ccir_dds.v
..............................\..............................\.........\................\.......\dve_ccir_dph.v
..............................\..............................\.........\................\.......\dve_ccir_fir.v
..............................\..............................\.........\................\.......\dve_ccir_lut.v
..............................\..............................\.........\................\.......\dve_ccir_mlt8x9.v
..............................\..............................\.........\................\.......\dve_ccir_top.v
..............................\..............................\.........\................\.......\dve_ccir_vtg.v
..............................\..............................\.........\Low_cost
..............................\..............................\.........\........\Verilog
..............................\..............................\.........\........\.......\dve_ccir_aps.v
..............................\..............................\.........\........\.......\dve_ccir_dds.v
..............................\..............................\.........\........\.......\dve_ccir_dph.v
..............................\..............................\.........\........\.......\dve_ccir_fir.v
..............................\..............................\.........\........\.......\dve_ccir_lut7b.v
..............................\..............................\.........\........\.......\dve_ccir_mlt.v
..............................\..............................\.........\........\.......\dve_ccir_mlt8x9.v
..............................\..............................\.........\........\.......\dve_ccir_top.v
..............................\..............................\.........\........\.......\dve_ccir_vtg.v
..............................\..............................\.........\........\.......\transcript

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