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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 134kb
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  • Author :土*****
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Introduction - If you have any usage issues, please Google them yourself
part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164.ALL ENTITY IS PORT (clk, sm, sb : IN mr bit, my, mg, br, by, bg : OUT bit) END traffic
Packet file list
(Preview for download)
unicntr
.......\cmp_state.ini
.......\db
.......\..\add_sub_1dh.tdf
.......\..\add_sub_rnh.tdf
.......\..\unicntr.asm.qmsg
.......\..\unicntr.cbx.xml
.......\..\unicntr.cmp.cdb
.......\..\unicntr.cmp.hdb
.......\..\unicntr.cmp.rdb
.......\..\unicntr.cmp.tdb
.......\..\unicntr.cmp0.ddb
.......\..\unicntr.db_info
.......\..\unicntr.eco.cdb
.......\..\unicntr.fit.qmsg
.......\..\unicntr.hier_info
.......\..\unicntr.hif
.......\..\unicntr.map.cdb
.......\..\unicntr.map.hdb
.......\..\unicntr.map.qmsg
.......\..\unicntr.pre_map.cdb
.......\..\unicntr.pre_map.hdb
.......\..\unicntr.psp
.......\..\unicntr.rpp.qmsg
.......\..\unicntr.rtlv.hdb
.......\..\unicntr.rtlv_sg.cdb
.......\..\unicntr.rtlv_sg_swap.cdb
.......\..\unicntr.sgate.rvd
.......\..\unicntr.sgdiff.cdb
.......\..\unicntr.sgdiff.hdb
.......\..\unicntr.sld_design_entry.sci
.......\..\unicntr.sld_design_entry_dsc.sci
.......\..\unicntr.syn_hier_info
.......\..\unicntr.tan.qmsg
.......\..\unicntr_cmp.qrpt
.......\unicntr.asm.rpt
.......\unicntr.done
.......\unicntr.fit.eqn
.......\unicntr.fit.rpt
.......\unicntr.fit.summary
.......\unicntr.flow.rpt
.......\unicntr.map.eqn
.......\unicntr.map.rpt
.......\unicntr.map.summary
.......\unicntr.pin
.......\unicntr.pof
.......\unicntr.qpf
.......\unicntr.qsf
.......\unicntr.qws
.......\unicntr.tan.rpt
.......\unicntr.tan.summary
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