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ceshixiangliang

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 11kb
  • Downloaded :0次
  • Author :陈***
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VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples--- corresponding Adder test vector (test bench). Txt
Packet file list
(Preview for download)
测试向量
........\测试向量(Test Bench)和波形产生:VHDL实例---8bit采样sine波形发生器.txt
........\测试向量(Test Bench)和波形产生:VHDL实例---加法器源程序.txt
........\测试向量(Test Bench)和波形产生:VHDL实例---波形发生器(含test beach).txt
........\测试向量(Test Bench)和波形产生:VHDL实例---相应加法器的测试向量(test bench).txt
........\测试向量(Test Bench)和波形产生:VHDL实例---经典双进程状态机(含test beach).txt
........\测试向量(Test Bench)和波形发生器:Verilog HDL 程序举例---8bit采样sine波形发生器.txt
........\测试向量(Test Bench)和波形发生器:Verilog HDL 程序举例---加法器源程序.txt
........\测试向量(Test Bench)和波形发生器:Verilog HDL 程序举例---相应加法器的测试向量(test bench).txt
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