a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.

8位全加器
.........\add1.asm.rpt
.........\add1.bsf
.........\add1.cdf
.........\add1.done
.........\add1.fit.eqn
.........\add1.fit.rpt
.........\add1.fit.summary
.........\add1.flow.rpt
.........\add1.map.eqn
.........\add1.map.rpt
.........\add1.map.summary
.........\add1.pin
.........\add1.pof
.........\add1.qpf
.........\add1.qsf
.........\add1.qws
.........\add1.sof
.........\add1.tan.rpt
.........\add1.tan.summary
.........\add1.vhd
.........\Block1.bdf
.........\cmp_state.ini
.........\db
.........\..\add1.asm.qmsg
.........\..\add1.cbx.xml
.........\..\add1.cmp.cdb
.........\..\add1.cmp.hdb
.........\..\add1.cmp.rdb
.........\..\add1.cmp.tdb
.........\..\add1.cmp0.ddb
.........\..\add1.db_info
.........\..\add1.eco.cdb
.........\..\add1.fit.qmsg
.........\..\add1.hier_info
.........\..\add1.hif
.........\..\add1.map.cdb
.........\..\add1.map.hdb
.........\..\add1.map.qmsg
.........\..\add1.pre_map.cdb
.........\..\add1.pre_map.hdb
.........\..\add1.psp
.........\..\add1.rtlv.hdb
.........\..\add1.rtlv_sg.cdb
.........\..\add1.rtlv_sg_swap.cdb
.........\..\add1.sgdiff.cdb
.........\..\add1.sgdiff.hdb
.........\..\add1.sld_design_entry.sci
.........\..\add1.sld_design_entry_dsc.sci
.........\..\add1.syn_hier_info
.........\..\add1.tan.qmsg
.........\..\add1_cmp.qrpt

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