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gongcehngsheji_477-2

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 6kb
  • Downloaded :0次
  • Author :李***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Packet file list
(Preview for download)
add1.vhd
add9.vhd
compare4to2.vhd
control.vhd
fifo3_inst.vhd
ksubabs.vhd
log_map_chip2.vhd
maxout.vhd
maxstartxt.vhd
ram_chip2.vhd
rom_chip1.vhd
suber.vhd
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