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frame_sync

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 24kb
  • Downloaded :1次
  • Author :刘***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Packet file list
(Preview for download)
frame_sync
..........\frame.cr.mti
..........\frame.mpf
..........\frame.v
..........\test_frame.v
..........\transcript
..........\vsim.wlf
..........\work
..........\....\frame
..........\....\.....\verilog.asm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\test_frame
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\_info
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