parity VERILOG source code for MODELSIM of a project. A test document.

parity
......\parity.cr.mti
......\parity.mpf
......\parity_decode.v
......\parity_encode.v
......\test_decode.v
......\test_encode.v
......\test_parity.v
......\vsim.wlf
......\work
......\....\parity
......\....\......\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\parity_decode
......\....\.............\verilog.asm
......\....\.............\_primary.dat
......\....\.............\_primary.vhd
......\....\parity_encode
......\....\.............\verilog.asm
......\....\.............\_primary.dat
......\....\.............\_primary.vhd
......\....\test
......\....\....\verilog.asm
......\....\....\_primary.dat
......\....\....\_primary.vhd
......\....\test_decode
......\....\...........\verilog.asm
......\....\...........\_primary.dat
......\....\...........\_primary.vhd
......\....\test_encode
......\....\...........\verilog.asm
......\....\...........\_primary.dat
......\....\...........\_primary.vhd
......\....\_info

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