basic unit of Verilog modules. Helpful for beginners.

verilog_code_673
................\add_beh.v
................\add_rtl.v
................\add_sim.v
................\afifo_beh.v
................\afifo_rtl.v
................\afifo_sim.v
................\checksum.v
................\check_sim.v
................\cnt_beh.v
................\cnt_rtl.v
................\cnt_sim.v
................\crc_beh.v
................\crc_rtl.v
................\crc_sim.v
................\dramcon_beh.v
................\dramcon_rtl.v
................\dramcon_sim.v
................\dual.v
................\dual_sim.v
................\encr_beh.v
................\encr_rtl.v
................\encr_sim.v
................\fpdramcon_beh.v
................\fpdramcon_rtl.v
................\fullcase.v
................\fullcase1.v
................\fullcase2.v
................\hamdec.v
................\hamgen.v
................\ham_sim.v
................\jk_beh.v
................\jk_rtl.v
................\jk_sim.v
................\lfsr2_beh.v
................\lfsr2_rtl.v
................\lfsr_beh.v
................\lfsr_rtl.v
................\lfsr_sim.v
................\mealy_beh.v
................\mealy_rtl.v
................\mono.v
................\mono2.v
................\mono_sim.v
................\moore2_rtl.v
................\moore_beh.v
................\moore_rtl.v
................\norace.v
................\onehot_rtl.v
................\opt.v
................\par.v
................\par_sim.v
................\pll_beh.v
................\pll_rtl.v
................\pll_sim.v
................\ram.v
................\ram_sim.v
................\sfifo_beh.v
................\sfifo_rtl.v
................\sfifo_sim.v
................\shift_beh.v
................\shift_rtl.v
................\shift_sim.v
................\smultiply1_rtl.v
................\smultiply2_rtl.v
................\smultiply3_rtl.v
................\smultiply_beh.v
................\smultiply_sim.v
................\sm_rom.v
................\sramcon_beh.v
................\sramcon_rtl.v
................\sramcon_sim.v
................\ssramcon_beh.v
................\ssramcon_rtl.v
................\ssramcon_sim.v
................\state_sim.v
................\template.v
................\transcript
................\umultiply1_rtl.v
................\umultiply2_rtl.v
................\umultiply3_rtl.v
................\umultiply_beh.v
................\umultiply_sim.v
................\um_rom.v

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