address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL

qep_data_bus
............\clk_4.v
............\clk_gen.v
............\cmp_state.ini
............\cnt_pulse.v
............\data_bus.v
............\data_bus_bak1115.v
............\db
............\..\add_sub_6sh.tdf
............\..\add_sub_bfg.tdf
............\..\add_sub_chh.tdf
............\..\qep_data_bus.asm.qmsg
............\..\qep_data_bus.atom.rvd
............\..\qep_data_bus.cbx.xml
............\..\qep_data_bus.cmp.cdb
............\..\qep_data_bus.cmp.hdb
............\..\qep_data_bus.cmp.rdb
............\..\qep_data_bus.cmp.tdb
............\..\qep_data_bus.cmp0.ddb
............\..\qep_data_bus.db_info
............\..\qep_data_bus.eco.cdb
............\..\qep_data_bus.eds_overflow
............\..\qep_data_bus.fit.qmsg
............\..\qep_data_bus.hier_info
............\..\qep_data_bus.hif
............\..\qep_data_bus.map.cdb
............\..\qep_data_bus.map.hdb
............\..\qep_data_bus.map.qmsg
............\..\qep_data_bus.pre_map.cdb
............\..\qep_data_bus.pre_map.hdb
............\..\qep_data_bus.psp
............\..\qep_data_bus.rpp.qmsg
............\..\qep_data_bus.rtlv.hdb
............\..\qep_data_bus.rtlv_sg.cdb
............\..\qep_data_bus.rtlv_sg_swap.cdb
............\..\qep_data_bus.sgate.rvd
............\..\qep_data_bus.sgdiff.cdb
............\..\qep_data_bus.sgdiff.hdb
............\..\qep_data_bus.sim.hdb
............\..\qep_data_bus.sim.qmsg
............\..\qep_data_bus.sim.rdb
............\..\qep_data_bus.sim.vwf
............\..\qep_data_bus.sld_design_entry.sci
............\..\qep_data_bus.sld_design_entry_dsc.sci
............\..\qep_data_bus.syn_hier_info
............\..\qep_data_bus.tan.qmsg
............\..\qep_data_bus_cmp.qrpt
............\..\qep_data_bus_sim.qrpt
............\disp.v
............\IO_Port.v
............\leospec.his
............\leospec.log
............\pwm_gen.v
............\qep4.v
............\qep_data_bus.asm.rpt
............\qep_data_bus.cdf
............\qep_data_bus.done
............\qep_data_bus.edf
............\qep_data_bus.fit.eqn
............\qep_data_bus.fit.rpt
............\qep_data_bus.fit.summary
............\qep_data_bus.fld
............\qep_data_bus.flow.rpt
............\qep_data_bus.map.eqn
............\qep_data_bus.map.rpt
............\qep_data_bus.map.summary
............\qep_data_bus.pin
............\qep_data_bus.pof
............\qep_data_bus.ppl
............\qep_data_bus.qpf
............\qep_data_bus.qsf
............\qep_data_bus.qws
............\qep_data_bus.sim.rpt
............\qep_data_bus.sof
............\qep_data_bus.sum
............\qep_data_bus.tan.rpt
............\qep_data_bus.tan.summary
............\qep_data_bus.tcl
............\qep_data_bus.v
............\qep_data_bus.vwf
............\qep_data_bus_debug.stp
............\serv_req_info.txt
............\sopc_builder_debug_log.txt
............\test.ptf
............\test.ptf.bak
............\test.v

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