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VHDL_processor

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 725kb
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  • Author :赵***
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Introduction - If you have any usage issues, please Google them yourself
use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Packet file list
(Preview for download)
VHDL_yuanlai
............\cmp_state.ini
............\cpu_mm_manager3.asm.rpt
............\cpu_mm_manager3.done
............\cpu_mm_manager3.fit.eqn
............\cpu_mm_manager3.fit.rpt
............\cpu_mm_manager3.fit.summary
............\cpu_mm_manager3.flow.rpt
............\cpu_mm_manager3.map.eqn
............\cpu_mm_manager3.map.rpt
............\cpu_mm_manager3.map.summary
............\cpu_mm_manager3.pin
............\cpu_mm_manager3.pof
............\cpu_mm_manager3.qpf
............\cpu_mm_manager3.qsf
............\cpu_mm_manager3.qws
............\cpu_mm_manager3.sim.rpt
............\cpu_mm_manager3.sof
............\cpu_mm_manager3.tan.rpt
............\cpu_mm_manager3.tan.summary
............\cpu_mm_manager3.vhd
............\cpu_mm_manager3.vwf
............\db
............\..\cpu_mm_manager3.asm.qmsg
............\..\cpu_mm_manager3.cmp.cdb
............\..\cpu_mm_manager3.cmp.ddb
............\..\cpu_mm_manager3.cmp.hdb
............\..\cpu_mm_manager3.cmp.rdb
............\..\cpu_mm_manager3.cmp.tdb
............\..\cpu_mm_manager3.dat_manager.dat
............\..\cpu_mm_manager3.db_info
............\..\cpu_mm_manager3.fit.qmsg
............\..\cpu_mm_manager3.hier_info
............\..\cpu_mm_manager3.hif
............\..\cpu_mm_manager3.icc
............\..\cpu_mm_manager3.map.cdb
............\..\cpu_mm_manager3.map.hdb
............\..\cpu_mm_manager3.map.qmsg
............\..\cpu_mm_manager3.pre_map.hdb
............\..\cpu_mm_manager3.project.hdb
............\..\cpu_mm_manager3.rtlv.hdb
............\..\cpu_mm_manager3.rtlv_sg.cdb
............\..\cpu_mm_manager3.rtlv_sg_swap.cdb
............\..\cpu_mm_manager3.sgdiff.cdb
............\..\cpu_mm_manager3.sgdiff.hdb
............\..\cpu_mm_manager3.signalprobe.cdb
............\..\cpu_mm_manager3.sim.hdb
............\..\cpu_mm_manager3.sim.qmsg
............\..\cpu_mm_manager3.sim.rdb
............\..\cpu_mm_manager3.sim.vwf
............\..\cpu_mm_manager3.sld_design_entry.sci
............\..\cpu_mm_manager3.sld_design_entry_dsc.sci
............\..\cpu_mm_manager3.syn_hier_info
............\..\cpu_mm_manager3.tan.qmsg
............\..\cpu_mm_manager3_cmp.qrpt
............\..\cpu_mm_manager3_sim.qrpt
............\Main_connect.vwf
............\sim.cfg
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