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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 145kb
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  • Author :hail****
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Introduction - If you have any usage issues, please Google them yourself
binary data or frequency signal selectors that the judgment low-frequency clock to meet conditions
Packet file list
(Preview for download)
mux2
....\cmp_state.ini
....\db
....\..\mux_2.asm.qmsg
....\..\mux_2.cbx.xml
....\..\mux_2.cmp.cdb
....\..\mux_2.cmp.hdb
....\..\mux_2.cmp.logdb
....\..\mux_2.cmp.rdb
....\..\mux_2.cmp.tdb
....\..\mux_2.cmp0.ddb
....\..\mux_2.db_info
....\..\mux_2.eco.cdb
....\..\mux_2.eds_overflow
....\..\mux_2.fit.qmsg
....\..\mux_2.fnsim.cdb
....\..\mux_2.fnsim.hdb
....\..\mux_2.hier_info
....\..\mux_2.hif
....\..\mux_2.map.cdb
....\..\mux_2.map.hdb
....\..\mux_2.map.logdb
....\..\mux_2.map.qmsg
....\..\mux_2.pre_map.cdb
....\..\mux_2.pre_map.hdb
....\..\mux_2.psp
....\..\mux_2.rtlv.hdb
....\..\mux_2.rtlv_sg.cdb
....\..\mux_2.rtlv_sg_swap.cdb
....\..\mux_2.sgdiff.cdb
....\..\mux_2.sgdiff.hdb
....\..\mux_2.signalprobe.cdb
....\..\mux_2.sim.hdb
....\..\mux_2.sim.qmsg
....\..\mux_2.sim.rdb
....\..\mux_2.sim.vwf
....\..\mux_2.sld_design_entry.sci
....\..\mux_2.sld_design_entry_dsc.sci
....\..\mux_2.syn_hier_info
....\..\mux_2.tan.qmsg
....\..\mux_2_cmp.qrpt
....\..\mux_2_sim.qrpt
....\mux_2.asm.rpt
....\mux_2.done
....\mux_2.fit.eqn
....\mux_2.fit.rpt
....\mux_2.fit.summary
....\mux_2.flow.rpt
....\mux_2.map.eqn
....\mux_2.map.rpt
....\mux_2.map.summary
....\mux_2.pin
....\mux_2.pof
....\mux_2.qpf
....\mux_2.qsf
....\mux_2.qws
....\mux_2.sim.rpt
....\mux_2.sof
....\mux_2.tan.rpt
....\mux_2.tan.summary
....\mux_2.vhd
....\mux_2.vwf
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